Zilog Z16C30 User Manual

Page 110

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Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

Select RICRHi=/INT Level

(RCmd:=0110): this command

conditions a channel so that subsequent accesses to the
MSByte of its Receive Interrupt Control Register (RICR15-
8) read or write the number of received characters at which
the channel starts requesting a Receive Data interrupt, as
described in Chapter 7. If software uses a Receive DMA
controller to store data in memory, it should disable Re-
ceive Data interrupts.

Select RICRHi=/RxREQ Level

(RCmd:=0111): this com-

mand conditions a channel so that subsequent accesses
to the MSByte of its Receive Interrupt Control Register
(RICR15-8) read or write the number of received charac-
ters at which the Receiver asserts /RxREQ to a Receive
DMA controller, as described in Chapter 6.

Select RICRHi=FIFO Status

(RCmd:=0101): this com-

mand conditions a channel so that reading the MSByte of
its Receive Interrupt Control Register (RICR15-8 yields the
number of characters in its RxFIFO. This is described more
fully in 'The Data Registers and the FIFOs' later in this
chapter.

Select Serial Data LSB or MSB First

(RTCmd:= 10100-

10101): these commands control whether a channel trans-
mits and assembles serial data with the Least Significant
or Most Significant bit going first on the line. “LSB first” is
the default after either a hardware or programmed reset,
and is the method used in most traditional data communi-
cations schemes. A channel applies this option as it
transfers data between the AD pins and the FIFOs. Be-
cause of this, these commands don’t affect functions like
matching addresses and sync characters and sending
syncs. This, in turn, means that software must program
such values “backward” in the TSR and RSR for “MSB first”
applications.

Select TICRHi=/INT Level

(TCmd:=0110): this command

conditions a channel so that subsequent accesses to the
MSByte of its Transmit Interrupt Control Register (TICR15-
8) read or write the number of empty TxFIFO entries at
which the Transmitter starts requesting a Transmit Data
interrupt, as described in Chapter 7. If software uses a
Transmit DMA controller to fetch data from memory, it
should disable Transmit Data interrupts.

Select TICRHi=/TxREQ Level

(TCmd:=0111): this com-

mand conditions a channel so that subsequent accesses
to the MSByte of its Transmit Interrupt Control Register
(RICR15-8) read or write the number of empty TxFIFO
entries at which the Transmitter asserts /TxREQ to a
Transmit DMA controller, as described in Chapter 6.

Select TICRHi=FIFO Status

(TCmd:=0101): this com-

mand conditions a channel so that reading the MSByte of
its Transmit Interrupt Control Register (TICR15-8) yields
the number of empty entries in its TxFIFO. This is described
more fully in 'The Data Registers and the FIFOs' later in this
chapter.

Send Abort

(TCmd:=1001): this command is valid only in

HDLC/SDLC mode and makes the Transmitter send an
Abort (Go Ahead) sequence. If the 2 MSBits of the
TxSubMode field of the Channel Mode Register (CMR15-
14) are 01, the Abort consists of a zero followed by 15
consecutive ones. Otherwise it consists of a zero followed
by seven ones. After sending the Abort, the Transmitter
operates as it would have after sending a closing Flag.
That is, if Wait2Send (TICR2) is 0 and there’s data in the
TxFIFO, it starts a new frame, otherwise it sends the Idle
condition defined by the TxIdle field (TCSR10-8).

Send Frame/Message

(TCmd:=1000): if the Wait2Send

bit in the Transmit Interrupt Control Register (TICR2) is 1,
the Transmitter waits between frames, sending the Idle
pattern defined by the TxIdle field of the Transmit Com-
mand/Status Register (TCSR10-8), until software issues
this command. The later section 'Synchronizing Frames/
Messages with Software Response' describes how this
feature differs from the one controlled by the Wait4TxTrig
bit in the Channel Control Register and the Trigger Tx DMA
command in RTCmd. On USCs manufactured after June
1993, this command also serves to release the interlock
that occurs if software sets the UnderWait bit (TCSR11) to
1, and a Tx Underrun condition occurs. See the section
‘Handling Overruns and Underruns’ later in this chapter.

In any case, this command releases an interlock that's
established after frame transmission, and is never needed
before the first frame after a Reset.

Set EOF/EOM

(TCmd:=1111): this command conditions a

channel so that it marks the next character, that software
or an external Transmit DMA controller writes to the Trans-
mit Data Register (TDR), as End of Frame/End of Message.
This marking makes the Transmitter perform the appropri-
ate closing actions after sending the character. (For ex-
ample, in HDLC/SDLC mode it sends a CRC and then a
closing Flag.) Typically, after issuing this command, soft-
ware should write the last character of the frame or mes-
sage to the LSByte of the Transmit Data Register (TDR7-0).
The channel automatically clears the state set by this
command when software (or a Transmit DMA controller)
writes to the TDR. Therefore this command applies to at
most one character.

UM009402-0201