Zilog Z16C30 - Manual (Page 18)

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Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
Table 1-1 Bus Interfacing Features of the USC (Chapter 2)
Multiplexed or Separate Address and Data Bus(es) can be selected for processor access to USC registers.
Read/Write Control Signals Separate Read and Write strobes, or Data strobe and Direction
control can be used. Only one set of signals should be
connected to the host processor; the other should be pulled
up.
8- or 16-Bit Data Bus DMA efficiency and bandwidth are doubled by using a 16-bit
bus, and software size and tediousness is improved as well.
With an 8-bit data bus and non-multiplexed Address and Data,
the bus pins that would otherwise be unused can be used for
register addressing from the processor.
Ready, Wait, or Acknowledge Handshaking can be selected for processor cycles. If Wait signalling is
selected, the USC drives Wait for interrupt acknowledge cycles
but not for register accesses — its 60 nanosecond register
access time is fast enough for no-Wait operation in almost all
applications. If Acknowledge signaling is selected, the part
drives the Acknowledge line for both interrupt acknowledge
cycles and register accesses.
Interrupt Acknowledge Cycles Separate inputs are provided for “Status line” vs. “pulse”
signalling. In the latter case single-pulse or double-pulse
cycles can be selected. The USC can also be used on buses
that don’t include Interrupt Acknowledge cycles.
Direct or Indirect Register Addressing The board designer can conserve the address space occu-
pied by the USC by requiring software to write register ad-
dresses into the USC, or can maximize software efficiency by
presenting register addresses directly. On a non-multiplexed
16-bit data bus, the latter choice requires external compo-
nents/logic to multiplex the low-order bits of the address onto
the AD pins.
Registers There are 32 16-bit registers in each channel of the USC,
including three selectable subregisters in the MSbyte of two of
them.
Big- or Little-Ending Byte Ordering Motorola or Intel style addressing can be selected for serial
data. Byte addressing within the USC’s 16-bit registers is
inherently Little-Endian/Intel style.
UM009402-0201