Zilog Z16C30 User Manual

Page 77

5-10

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.6.1 Break Conditions

A Break condition is a period of Space (zero) state on an
Async line, that’s longer than the length of a character.
Such a sequence traditionally signals an exceptional con-
dition or a desire to stop transmission in the opposite
direction. Alternatively, a Break may mean that the switched
or physical connection with the other station is broken. The
Receiver detects a Break condition when it samples a
supposed Stop bit as Space/zero (a Framing Error) and all
the data bits were also Space/zero. In this case the
Receiver doesn’t place the all-zero character in the RxFIFO,
but instead sets the Break/Abort bit in the Receive Com-
mand/Status Register (RCSR5). This bit can be enabled to
cause an interrupt at the start of a Break.

If it's necessary to have an interrupt at the end of a Break,
software can switch the Receiver to Monosync mode,
looking for an all-ones Sync character, and arm the Exited
Hunt condition to flag the end of the Break. After the

interrupt, software has to switch back to async mode and
purge the Rx FIFO. Alternatively, software can tell when the
Break ends by polling the Break/Abort bit. The bit doesn’t
go back to 0 until software has written a 1 to the bit to
“unlatch” it, and RxD has gone back to 1/High/Mark.

Software can send a Break by programming the TxDMode
field of the Input/Output Control Register (IOCR7-6) to 10
to force TxD to low/space. Then it can use whatever kind
of timing resources it has available to measure the desired
duration of the Break. After this, it can program TxDMode
back to 11 to force TxD to high/mark or to 00 to resume
normal operation. Chapter 4 describes a channel’s Counters
and Baud Rate Generators that may be useful in timing the
length of a transmitted Break. While most modern serial
controllers will detect a Break that’s only slightly longer
than a character, older conventions required a Break to be
much longer: 200 milliseconds or more.

5.7 ISOCHRONOUS MODE

Software can select Isochronous operation for the Trans-
mitter and the Receiver, by programming the TxMode and
RxMode fields (CMR11-8 and CMR3-0 respectively) to
0010. This mode is similar to Asynchronous mode as
described above, except that the Transmitter and Re-
ceiver use 1X instead of 16x, 32x, or 64x clocking. This
typically means that an external bit clock must be pro-
vided. It’s possible to use the DPLL to recover a 1x clock,
but this is a lot like what the Receiver does in Async mode
anyway.

Of the options available in the Channel Mode Register for
Async mode, the only one that applies in Isochronous
mode is CMR14. This controls whether the Transmitter
sends one or two stop bits:

CMR14

Length of Tx Stop

1 bit time

2 bit times

The USC doesn’t use the other three bits of the TxSubMode
field in Isochronous mode, nor any of the RxSubMode bits,
but Zilog reserves these bits for functional extensions in
future products. Software should always program them
with zeroes in Isochronous mode on a USC.

UM009402-0201