Zilog Z16C30 User Manual

Page 103

5-36

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.19 DMA SUPPORT FEATURES

(Continued)

If software has enabled the RCC, and a frame or message
ends when the RCC FIFO is already full, the new value
overwrites its predecessor, and the three oldest entries are
not affected. The channel remembers this event in a status
bit that it routes through the RCC FIFO, much like it routes
other status bits through the RxFIFO. When software reads
the preceding entries so that an overwriting/overwritten
entry becomes the oldest one in the RCC FIFO, the channel
sets the

RCCFOvflo

bit in the Channel Command/Status

Register (CCSR15). Once RCCFOvflo is set, the only way
to clear it (other than to Reset the whole channel) is to write
a 1 to the

ClearRCCF

bit (RCCR13), or, for USCs manufac-

tured after June 1993, by writing a Purge Rx command to
the RTCmd field (CCAR15-11). Either of these actions also
empties the RCC FIFO and clears RCCFAvail.

Writing to the RCCFOvflo and RCCFAvail bits has no
effect, nor does writing a 0 to the ClearRCCF bit. ClearRCCF
always reads as 0.

5.19.3 Transmit Control Blocks

Figure 5-16 shows the Channel Control Register. Its

TxCtrlBlk

field (CCR15-14) controls what the Transmitter

does with the first 32 bits of data that an external Transmit
DMA controller fetches from memory at the start of a frame
or message. (While software can use Transmit Control
Blocks when it fills the TxFIFO, there’s no obvious reason
to do so, compared to just writing the control registers
directly.) The Transmitter interprets TxCtrlBlk as follows:

TxCtrlBlk

Kind of TCB’s used

No Transmit Control Block

32-bit Transmit Control Block

Reserved; do not program

When TxCtrlBlk is 10, a channel treats the next 32 bits that
software or an external Transmit DMA controller writes to
the TDR, as a Transmit Control Block after any of the
following happen:

After software writes a Trigger Tx DMA (or Trigger Tx
and Rx DMA) command to the RTCmd field of the
Channel Command/Address Register, or

After software writes a Load TCC (or Load RCC and
TCC) command to RTCmd, or

After software writes a Purge Tx FIFO (or Purge Tx and
Rx FIFO) command to RTCmd, or

After the Transmit DMA controller (or software) writes
data into the TxFIFO that decrements the TCC to zero.
As noted earlier, the Transmitter drops its DMA re-
quest from the time the DMA controller fetches the last
character of a frame, until after it moves the character
to its shift register. It does this so that the DMA
controller doesn’t fetch the Transmit Control Block for
the next frame or message, while the Transmitter still
needs the control information for the current frame.

Note that this list does NOT include hardware or software
Reset. This means that after either kind of Reset, the
Transmitter is not expecting a TCB. Software must issue
one of the commands listed above to condition it to receive
the TCB for the first transmit frame after a Reset.

Figure 5-17 shows a 32-bit Transmit Control Block as part
of a sequence of 16-bit words in memory. The MS 4 bits of
the first word (or the only word in a 16-bit TCB) define a new
TxSubMode value for the following transmit data. A chan-
nel writes these bits into the TxSubMode field of its Channel
Mode Register (CMR15-12) without changing the rest of
the CMR. Bits 4-2, of the first or only word, define the
TxResidue value for the following frame in HDLC/SDLC or
HDLC/SDLC Loop mode. The channel writes these bits
into the TxResidue field of the Channel Command/ Status
Register (CCSR4-2) without affecting the rest of the CCSR.
The channel ignores bits 11-5 and 1-0 of the first or only
word, but Zilog reserves these bits for future enhance-
ments and software should ensure that they’re all zero.

A channel transfers the second word of a 32-bit TCB
through the Transmit Count Limit Register (TCLR) and into
the TC Counter (TCCR). Therefore this word should con-
tain the number of characters/bytes that follow this TCB,
until the end of the frame or message. As noted in the
earlier section on Transmit Character Counter, the TCC is
loaded from the TCLR only when software writes one of
three commands to the device, or when the 2nd word of a
32-bit TCB is fetched. This means that if software wants the
hardware to handle multiple transmissions without soft-
ware intervention, 16-bit TCBs aren't useful.

Figure 5-17 shows a TCB in the middle of a memory buffer,
that is, directly following the last characters of the previous
frame. Perhaps more typically, the TCB would be the first
four bytes of a memory buffer dedicated to this frame or
message.

UM009402-0201