Zilog Z16C30 - Manual (Page 111)

5-44
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
5.20 COMMANDS (Continued)
Trigger Channel Load DMA (RTCmd:=00100): Chapter 7
will describe how this command puts a channel in a special
mode in which an external Transmit DMA controller can
initialize all the registers in the channel. Software must
program and set up an external Transmit DMA controller
as for transmitting data, before it issues this command.
Trigger Rx and/or Tx DMA (RTCmd:=00101-00111): if
one of the Wait4xxTrig bits in a channel’s Channel Control
Register (CCR13 for Tx, CCR5 for Rx) is 1, the channel
stops requesting that kind of DMA transfer after the end of
each frame. When this happens, software should use one
of these commands to reenable requests to the external
DMA controller(s), for the next frame. These commands
also load the Receive and/or Transmit Character Counter
from the Receive and/or Transmit Count Limit Register
(RCC from RCLR and/or TCC from TCLR). This may enable
or disable character counting. If software has enabled the
Transmit Control Block feature in the TxCtrlBlk field of the
Channel Control Register (CCR15-14=01 or 10), a Trigger
Tx DMA or Trigger Tx and Rx DMA command also condi-
tions the Transmitter to treat the next 16 or 32 bits written
to the Transmit Data Register as a TCB. The later section
'Synchronizing Frames/Messages with Software Response'
describes how this feature differs from the one controlled
by the Wait2Send bit in the Transmit Interrupt Control
Register and the “Send Frame/Message” command in
TCmd.
The two commands above release interlocks that occur at
the end of a frame, and are never needed before the first
frame after a Reset.
5.21 RESETTING A USC CHANNEL
Figure 5-19 shows the RTReset bit in the Channel Com-
mand/Address Register (CCAR10). Software can use this
bit to reset a channel to a known and inactive state like that
produced by driving the /RESET pin low. (The most signifi-
cant difference is that the USC requires software to write
the Bus Configuration Register (BCR) after a hardware
Reset, but not after this kind of “software Reset”.)
To software-reset a channel when using a 16-bit data bus:
1. Write CCAR (or its MSByte) with RTReset=1.
2. Write a 16-bit zero to CCAR.
To software-reset a channel when using an 8-bit bus:
1. Write the MSByte of CCAR with RTReset=1.
2. Write the LSByte of CCAR with an 8-bit zero.
3. Write the MSByte of CCAR with an 8-bit zero.
The way this “software reset” works is that the 1 state of
RTReset conditions the channel’s register address decod-
ing logic so that the subsequent write operation actually
writes data into all the registers in the channel. Between the
time that software writes RTReset as 1, and when it writes
it back to 0, the channel doesn’t drive I/O pins, it either tri-
states output pins or holds them in their inactive state, but
register bits that don’t directly affect these pins are un-
changed/undefined.
Leaving the RTReset bit set is a common mistake made
by first-time users of a USC family member.
UM009402-0201