15 hdlc/sdlc loop mode (continued), 16 cyclic redundancy checking (crc) – Zilog Z16C30 User Manual

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5-22

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.15 HDLC/SDLC LOOP MODE

(Continued)

OnLoop stays 1 unless the part is reset or software pro-
grams the TxMode field to a different value. Once OnLoop
is 1 and the channel is repeating data from RxD to TxD,
CMR13 controls what the Transmitter does when it re-
ceives a(nother) Go Ahead sequence. If CMR13 is 0, the
channel just keeps repeating data, including the “GA”. If
CMR13 is 1 when the Receiver detects another “Go Ahead”,
the Transmitter changes the last bit of the GA from 1 to 0
(making it a Flag), sets the

LoopSend

bit (CCSR6) and

proceeds to start sending data. (If there’s no data available
in the TxFIFO it keeps sending Flags, otherwise it sends the
data in the TxFIFO.)

When the Transmitter has been sending data and encoun-
ters either a character marked as “EOF/EOM”, or an
underrun condition when CMR15=1, CMR13 determines
how it proceeds. If CMR13 is 1 in either of these situations,
the Transmitter stays active and sends Flags or additional
frames as they become available in the TxFIFO. If CMR13
is 0 after the channel has sent a closing Flag or an idle Flag,
it clears the LoopSend (CCSR6) bit and returns to repeat-
ing data from RxD onto TxD.

CMR12 controls whether the Transmitter sends idle Flags
with shared zero bits, as described for normal HDLC/
SDLC mode.

5.16 CYCLIC REDUNDANCY CHECKING (CRC)

A USC channel will send and check CRC codes only in
synchronous modes, namely External Sync, Monosync,
Slaved Monosync, Bisync, Transparent Bisync, HDLC/
SDLC, HDLC/SDLC Loop, and 802.3 modes.

The

TxCRCType

and

RxCRC

Type fields in the Transmit

and Receive Mode Registers (TMR12-11 and RMR12-11)
control how the Transmitter and Receiver accumulate
CRC codes.

00 in either field selects the 16-bit CRC-CCITT polynomial
x

+1. In HDLC, HDLC Loop, and 802.3 modes, the

Transmitter inverts each CRC before sending it, the Re-
ceiver checks for remainders of F0B8

, and the TxCRCStart

and RxCRCStart bits should be programmed as 1 to start
the CRC generators with all ones. In other synchronous
modes the Transmitter sends accumulated CRCs normally
and the Receiver checks for all-zero remainders.

01 in either field selects the CRC-16 polynomial x

+1. The Transmitter sends accumulated CRCs nor-

mally and the Receiver checks for all-zero remainders.
This choice is not compatible with HDLC, HDLC Loop, and
802.3 protocols, and in these modes CRC-16 will not
operate correctly even between USC family Transmitters
and Receivers.

10 in TxCRCType or RxCRCType selects the 32-bit Ethernet
polynomial x

+x+1. In HDLC, HDLC Loop, and 802.3 modes, the

Transmitter inverts each CRC before transmitting it, the
Receiver checks for remainders equal to C704DD7B

and the TxCRCStart and RxCRCStart bits should be pro-
grammed as 1 to start the CRC generators with all ones. In
other synchronous modes the Transmitter sends CRCs
normally and the Receiver checks for all-zero remainders.

Zilog reserves the value 11 in TxCRCType or RxCRCType
for future product enhancements; it should not be pro-
grammed.

The

TxCRCStart

and

RxCRCStart

bits (TMR10 and

RMR10) control the starting value of the Transmit and
Receive CRC generators for each frame or message. A 0
in this bit selects an all-zero starting value and a 1 selects
a value of all ones. In HDLC, HDLC Loop, and 802.3 modes
these bits should be 1.

The Transmitter and Receiver automatically clear their
CRC generators to the state selected by these CRCStart
bits at the start of each frame. The Transmitter does this
after it sends an opening Sync or Flag sequence. The
Receiver does so each time it recognizes a Sync or Flag
sequence (it may be the last one before the first character
of the frame or message). For special CRC requirements,
the

Clear Rx CRC

and

Clear Tx CRC

commands give

software the ability to clear the CRC generators at any time.
See the later section 'Commands' for a full description of
these operations.

The

TMR10

and

RMR10

bits (TMR9 and RMR9) control

whether the channel processes transmitted and received
characters through the respective CRC generators. A 0
excludes characters from the CRC while a 1 includes
them. The Transmitter captures the state of TxCRCEnab
with each character as it’s written into the TxFIFO, so that
software can change the bit dynamically for different
characters.

UM009402-0201