Zilog Z16C30 - Manual (Page 60)

4-11
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
The RTMode field of the Channel Command/Address
register (CCAR9-8) controls the relationship between the
Transmitter and the Receiver and thus between the TxD
and RxD pins. It is encoded as follows:
RTMode Operation
00 Normal operation: the Transmitter and
Receiver are completely independent.
01 Echo mode: the state of the RxD pin is
copied directly onto the TxD pin. Data
from the Transmitter is ignored.
10 Pin Controlled Local Loop: the data from
the TxD pin, as determined by the
TxDMode field (IOCR7-6), is routed to the
Receiver rather than the data from RxD. If
TxDMode specs TxD as high impedance,
the Receiver can take its input from a
remote source via TxD rather than RxD.
11 Internal Local Loop: the data from the
Transmitter is routed to the Receiver rather
than the data from RxD, regardless of the
setting of the TxDMode field (IOCR7-6).
4.7 EDGE DETECTION AND INTERRUPTS
Software can program each channel to detect rising and/
or falling edges on the /CTS, /DCD, /TxC, /RxC, /TxREQ,
and /RxREQ pins, and to interrupt when such events
occur. Figure 4-7 shows that the Status Interrupt Control
Register (SICR) includes separate Interrupt Arm (IA) bits
for rising and falling edges on each of these pins. (Chapter
7 describes the USC’s interrupt features in detail.) A 1 in
one of these bits makes the channel detect that kind of
edge, while a 0 makes it ignore such edges. This edge
detection and interrupt mechanism operates without re-
gard for whether the various pins are programmed as
inputs or outputs in the I/O Control Register (IOCR).
When a channel detects an edge that’s enabled in the
SICR, it records the event in an internal “edge detection
latch” for that input. This latch is not directly accessible in
the USC’s register map. Instead, as shown in Figure 4-8,
the Miscellaneous Interrupt Status Register (MISR) in-
cludes two bits for each of these six pins, one called a
“Latched/Unlatch” or L/U bit, and the other being a “data
bit” that has the same name as the pin itself.
A hardware or software Reset sequence clears all the L/U
bits to zero. While the L/U bit for a pin is 0, the associated
data bit reports and tracks the state of the pin in a
“transparent” fashion, with a 1 indicating a low and a 0
indicating a high.
Whenever a pin’s L/U bit is 0 and its internal edge-
detection latch is set, the channel sets the L/U bit to 1,
clears the detection latch, and sets the I/O Pin Interrupt
Pending (IOP IP) bit. IOP IP can be read and cleared (and
if necessary set) in the Daisy Chain Control Register
(DCCR1). Chapter 7 describes how the I/O Pin Enable and
Master Interrupt Enable bits determine whether the IP bit
actually results in an interrupt request to the processor.
UM009402-0201