Zilog Z16C30 - Manual (Page 206)

B-12
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
INTERRUPT QUESTIONS AND ANSWERS
DMA QUESTIONS AND ANSWERS (Continued)
Q: Why is the /BIN input sampled twice in the IUSC?
/BIN is a bus grant, and if /BUSREQ is sent, why should
more than one bus grant be required? It would appear
that at the end of a transfer, /BIN goes high early
enough so that a device does not become confused
by the /BIN being low for another device’s transfers.
A: This allows the arbitration mechanism to present a
high-performance but, occasionally, metastable grant
to the IUSC. The IUSC takes a while to get the state
machine going. And these start-up steps occur be-
tween the two samples. You can view at the second
sample as a confirming one, just before the IUSC starts
active operation.
Q: My system sometimes locks up after trying to add
entries to a Linked List. What is going on?
A: The most likely cause is an interlock problem with the
process and DMA accessing the byte count in the last
entry in the List. There is a specific way to add entries
to the List under these circumstances. It is detailed in
the IUSC Technical Manual.
Q: When does the /W//RDY signal go tri-state?
A: The /W//RDY never goes tri-state as an output, but is
only driven High or Low. When acting as an input, its
AC characteristic is the same as a tri-stated output. As
stated in the Tech Manual, if several devices are in the
board, the hardware must logically combine the
/W//RDY pins. In the IUSC the /W//RDY pin is released
from the driven condition (goes tri-state at the same
time that the bus control signals are driven by the
IUSC. In a similar fashion, the /W//RDY pin is returned
to a driven state when the bus controls are tri-stated by
the IUSC. This pin will always return High; it only goes
Low in response to some kind of bus cycle. For Wait
mode it only goes Low during interrupt acknowledge
cycles, and in Ready mode it goes Low for any access
of the IUSC as a slave.
Q: Why is it necessary to disable interrupts (as with the
SCC) to do address demultiplexing from data?
A: It is prudent to disable interrupts when doing the
“address point” operation because if the pointer is
pointing at an address and an interrupt for that channel
comes, the service routine will disrupt the pointer and
then return to the main program without restoring the
pointer, which will disrupt the USC’s normal operation.
Note that because the USC contains a pointer per
channel, only the channel being “pointed to” needs to
have its interrupts disabled.
Q: When an overrun condition occurs, will the USC con-
tinue to assert the DMA request until the FIFO is
purged, or will the DMA request be disabled after the
maximum number of characters specified by initial
value of RCLR have been transferred out of the Rx
FIFO (that is in case the Rx FIFO is not able to be
purged in time)?
A: When the overrun data enters the Rx FIFO, the USC will
not recognize it until it reaches the top of the Rx FIFO.
The DMA will continue to transfer data until the overrun
data reaches the top of the Rx FIFO. Then the overrun
interrupt is generated and the recovery process be-
gins with software.
Q: Why and when should an Interrupt Pending (IP) bit be
cleared?
A: IP bits should be cleared so that another incoming
interrupt can be requested while the current interrupt
is serviced. IP bits can be cleared at the beginning or
the end of the interrupt routine.
Q: An abort is received on the 4th byte in the middle of a
Rx frame. Is abort marked after the 3rd byte?
A: The fourth byte is tagged with both RxBound and Abort
if the Abort Frame option is programmed in the RMR.
Otherwise the Abort condition is reported immediately
and the software must read out the Rx FIFO until the
RxBound byte is found, checking the CRC results at
the same time.
Q: What happens if the received frame is shorter than the
programmed Rx Interrupt or Rx Request Level? Will
the USC family request any kind of interrupt or DMA
transfer?
A: The USC family will request an Rx data interrupt when
the byte tagged with RxBound is written into the FIFO.
In the interrupt routine, one must check the number of
bytes in the Rx FIFO. Read those bytes out of the FIFO.
When the byte tagged with RxBound is the oldest byte
in the FIFO, the USC will request a Rx Status interrupt.
(The Rx Stat IP in the DCCR will be set, and the
RxBound bit in the RCSR will be set).
UM009402-0201