Zilog Z16C30 - Manual (Page 48)

3-4
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
3.1 INTRODUCTION (Continued)
U7-9 are octal latches that capture the address from the
186 and present the latched address to the RAMs and
EPROMs. The EPROMs are selected by the Upper Chip
Select (/UCS) output of the 186, while the RAMs are
selected by the Lower Chip Select (/LCS) output. The USC
resides in I/O space, one channel being selected by the
first of the 186' Peripheral Chip Select outputs (PCS0) and
the other channel being selected by the other (PCS1).
The 28-pin EPROM sockets are set up to accept 2764’s,
27128’s, 27256’s, or 27512’s. The 32-pin RAM sockets can
accept 32-pin 128Kx8 or 28-pin 32Kx8 static RAMs.
The U10 74FCT240 inverts signals between active-high
signals on the 186 and active-low signals on the USC. The
/TxREQ and /RxREQ pins of USC channel A are inverted to
make the DMA Request 0 and 1 inputs of the 80186'
integrated DMA channels. This means that USC channel A
can use DMA operation while USC channel B must be
interrupt-driven or polled. Since the 186' DMA channels
use flow-through (two cycle) operation, channel A’s
/TxACK and /RxACK pins are free for use in the serial
interfaces.
The U11 PAL16L8 provides some glue logic, as follows:
/UCS =/PCS0 + /PCS1 ;active-low OR of chip selects
/NMI =/NO
+/NMI * NC
;debounce latch for NMI
pushbutton
/SWRE =/SWR * /A0 ;write strobe for even-ad-
dressed (LS) RAM
/SWRO =/SWR * /BHE ;write strobe for odd-ad-
dressed (MS) RAM
/INT0 =UAINT * UBINT ;OR two active-low interrupt
Requests to make high-ac-
tive output
In these equations, “*” indicates a logical AND operation,
“+” indicates a logical OR, and “/” indicates negation or a
Low state.
All of the USC’s serial interface pins are shown on its right
side in Figure 3-1, and appear again on the J3 and J4
jumper headers at the upper right of Figure 3-2. From there
they can be connected in various ways, either jumpered
back among J3 and J4, or connected to the serial inter-
faces via the J5 and J6 jumper headers.
J5 leads to two MAX238 RS232 driver-receivers, whose
opposite sides are connected to the user’s choice of an
RS-232 DB25 arranged “DTE” style or “DCE” style.
Similarly, J6 leads to 75ALS194 RS-422 differential drivers
and 75ALS195 RS-422 differential receivers, whose oppo-
site sides are connected to the user’s choice of an RS-530
DB25 arranged “DTE” style or “DCE” style, or to a DIN
Circular-8 connector arranged as a LocalTalk (Appletalk)
interface. When using an RS-530 interface, jumper the J7
3-pin header between pins 2 and 3, for Appletalk jumper
it between 1 and 2 and connect a “Data Terminal Ready”
signal (typically Tx Acknowledge) to pin 5 of J6.
The following signals are typically jumpered straight across
between (J3 or J4) and (J5 or J6):
Pin Signal Serial Interface Signal
1 USC TXD —> DTE TxD or DCE RxD
2 USC RXD <— DTE Rx Data or DCE Tx Data
3 USC /RxACK —> DTE Request to Send or DCE
Clear to Send
4 USC /CTS <— DTE Clear to Send or DCE
Request to Send
5 USC /TxACK —> DTE Data Terminal Ready or
DCE Data Set Ready
The connection of other signals is more flexible and appli-
cation-dependent. The possibilities include, but are not
limited to:
USC J3/4 J5/6
pin pin pin Serial interface Signal
/DCD 6 7 —> DCE Data Carrier Detect
/DCD 6 8 <— DTE Data Carrier Detect
/RxC 8 11 —> DCE Rx Clock
/RxC 8 12 <— DTE Rx Clock
/TxC 9 13 —> DTE Tx Clock (DTE source)
or DCE Tx Clock (DCE source)
/TxC 9 14 <— DTE Tx Clock (DCE source)
or DCE Tx Clock (DTE source)
/TxREQ 11 15 —> DCE Ring Indicator
(see note 1)
/TxREQ 11 16 <— DTE Ring Indicator
(see note 1)
/RxREQ 12 6 <— DTE Data Set Ready or
DCE Data Terminal Ready
(see note 1)
Note 1: For channel A, these J3 pins should be connected
only if they are not used as DMA Requests.
UM009402-0201