Zilog Z16C30 - Manual (Page 151)

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Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
The Vector Includes Status field (VIS; ICR12-9) controls
whether the vector, that the channel returns during an
interrupt acknowledge cycle in which the highest-priority
requesting type is in the channel, identifies the type or not.
Such vector modification can be enabled for all types in the
channel, or only for those above a selected priority level:
VIS Which types appear in vectors
0xxx No types
100x All types
1010 IOP and above (not Misc)
1011 Transmit Data and above
1100 Transmit Status and above
1101 Receive Data & Status
1110 Receive Status only
1111 No types
If the contents of VIS allow the highest-priority type, that’s
requesting at the time of an Interrupt Acknowledge cycle,
to modify the interrupt vector, then bits 3-1 of the returned
vector identify that type as described in the next section.
If not, the channel returns the 8-bit vector exactly as the
host software programmed it.
7.15 INTERRUPT VECTORS
Software can read and write a channel’s interrupt vector
information in the Interrupt Vector Register (IVR). This
register is also the basis of the vector that the channel
returns during an interrupt acknowledge cycle in which the
highest priority requesting type is in the channel.
Figure 7-18 shows the IVR. The basic vector can be written
and read in its LSByte; software can read a modified
version of the vector in its MSByte. (Writing the MSByte has
no effect.) Bits 15-12 and 8 are the image of those in the
corresponding bits of the LSByte, while the
TypeCode
field (IVR11-9) gives the identity of the highest priority
interrupt type that has its IP bit set (the state of its IUS bit
doesn’t matter).
TypeCode Meaning
000 No interrupt pending
001 Miscellaneous
010 I/O pin
011 Transmit Data
100 Transmit Status
101 Receive Data
110 Receive Status
111 (will not be read)
The state of the VIS field (ICR12-9) has no effect on reading
the IVR. VIS simply controls how the channel decides
whether to return IVR15-8 or IVR7-0 as the interrupt vector
when it responds to an interrupt acknowledge cycle.
UM009402-0201