Zilog Z16C30 User Manual

Page 20

1-7

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

Table 1-3. Serial Controller Features of the USC

Major Protocol Categories

Chapter 4 begins with a small tutorial on the differences between Asynchronous,
Character-Oriented Synchronous, and Bit-Oriented Synchronous (Packet)
protocols.

Asynchronous Protocols

In addition to classic Async, the USC can handle the following variations:

■

Isochronous (1X rather than 16-64X clock)

■

Nine-Bit (Address Wake-up — an extra bit signifies Address/Data)

Character-Oriented
Synchronous Protocols

■

External Sync (Receive only: simple character assembly)

■

Monosync (1-character sync pattern, no hardware framing)

■

Bisync (2-character sync pattern, no hardware framing)

■

Transparent Bisync (Bisync + hardware support for Transparency)

■

Slaved Monosync (Xmit only; X.21 Tx character alignment to Rx)

■

IEEE 802.3 (Ethernet; requires external collision detect and backoff)

Bit-Oriented Synchronous
Protocols

■

HDLC/SDLC

■

HDLC/SDLC Loop (RxD is repeated on TxD except when Xmit is
enabled and triggered by a received Go Ahead/Abort sequence)

Character Length

is programmable from 1 bit/character to:

■

8 bits including Parity, if any, in synchronous modes

■

8 bits plus Parity, if any, in Async mode

■

8 bits plus Parity plus the Address/Data bit in Nine-Bit mode

CRC Generation/Checking

In synchronous modes, the USC will generate and check CRC-CCITT, CRC-16, or
CRC-32 codes for each frame or message. For character-oriented modes other
than 802.3, software can selectively control which characters are included in the
CRC, for both transmitting and reception. For HDLC/SDLC and 802.3, CRC status
can be stored in memory for each received frame.

Parity Checking

Asynchronous or Synchronous modes. Odd/Even/Mark/Space/None.

Transmit Status Reporting

Optional interrupt on: Preamble Sent, Idle Sent, Abort Sent, End of Frame/
Message, CRC Sent, Underrun No interrupt: All Sent, Tx Empty

Receive Status Reporting

Optional Interrupt on: Exited Hunt, Idle Received, Break, Abort (immediate or
synchronized with the RxFIFO), Rx Boundary (end of frame/message), Parity
Error, Overrun. No interrupt: Short Frame, Code Violation Type, CRC Error,
Framing Error, Rx Character Available

Character Counters

These 16-bit counters decrement for each character received or fetched from
memory for transmission. The Tx CC can control the length of Tx frames in
synchronous modes using DMA. The Rx CC tracks the length of each Rx frame
in synchronous modes using DMA, and optionally interrupts in case an Rx frame
is too long.

RCC FIFO

A four-deep store for ending Rx Character Counter values for each frame.

UM009402-0201