Zilog Z16C30 User Manual

Page 97

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Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.18 STATUS REPORTING

(Continued)

This bit is not associated with a particular point in the
received data stream, for either the Break or Abort condi-
tion. (But see the description of “Abort/PE” below for an
Abort indication that is queued with Receive data.)

A channel can request an interrupt when this bit goes from
0 to 1 if the Break/Abort IA bit in the Receive Interrupt
Control Register (RICR5) is 1. Software must write a 1 to
Break/Abort to unlatch it, and to allow further interrupts if
RICR5 is 1; writing a 0 has no effect. In async modes, a
channel doesn’t actually clear RCSR5 until software has
written a 1 to unlatch it, and RxD has gone to 1 to end the
break condition.

RxBound:

The Receiver queues this bit through the RxFIFO

with each received character. It sets the bit with a charac-
ter that represents the boundary of a logical grouping of
data, but this indication isn’t visible to software until the
character is the oldest one in the RxFIFO, or the second-
oldest with WordStatus=1.

As described earlier in this Status Reporting section,
RCSR4 may represent an interrupt bit, or the status asso-
ciated with the oldest 1 or 2 character(s) still in the RxFIFO;
or may be 1 if a RxBound character was just read from the
RxFIFO. Since the Receive Status Block feature stores the
RCSR in memory after each character that the Receiver
marks with this bit set, a Receive Status Block always
shows RxBound as 1.

In HDLC/SDLC mode the Receiver sets RxBound for the
last complete or partial character before an ending Flag or
Abort. In Transparent Bisync mode it sets this bit for an
ENQ, EOT, ETB, ETX, or ITB character that follows a DLE.
In External Sync or 802.3 (Ethernet) mode the Receiver
sets this bit for the character just completed or partially
assembled when the /DCD pin went High. In Nine-Bit
mode it sets this bit for an address character. Note that the
Receiver never sets this bit in other modes, including
Monosync and Bisync modes.

A channel can request an interrupt when software or a
DMA channel reads a character from the RDR that has this
bit set, if the RxBound IA bit in the Receive Interrupt Control
Register (RICR4) is 1. In this case software must write a 1
to RxBound to unlatch it and allow further interrupts; writing
a 0 has no effect.

CRCE/FE:

The Receiver queues this bit through the RxFIFO

with each received character. RCSR3 may represent the
status at the time that a RxBound character was read from
the RxFIFO, or the status associated with the oldest 1 or 2
character(s) still in the RxFIFO, as described earlier in this
Status Reporting section. In a stored Receive Status Block
it represents the status of the previous character, which in
turn represents the CRC-correctness of the frame in 802.3
and HDLC/SDLC modes.

In synchronous modes the Receiver makes CRCE/FE 0 if
its CRC checker showed “correct” status when it stored the
character in the RxFIFO, or 1 if the CRC checker wasn’t
correct. See the earlier section Cyclic Redundancy Check-
ing for more information. In asynchronous, isochronous, or
Nine-Bit mode, the Receiver makes this bit 1 to show a
Framing Error if it samples the associated character’s Stop
bit as 0.

Abort/PE:

The Receiver queues this bit through the RxFIFO

with each received character. RCSR2 may represent an
interrupt bit, or the status at the time that a RxBound
character was read from the RxFIFO, or the status associ-
ated with the oldest 1 or 2 character(s) still in the RxFIFO,
as described earlier in this Status Reporting section. In a
stored Receive Status Block it may represent an interrupt
bit or the status of the previous 1 or 2 character(s).

If the

QAbort

bit in the Receive Mode Register (RMR8) is

0, the Receiver sets this bit to show a Parity Error for a
character if the RxParEnab bit (RMR5) is 1 and the
character’s parity bit doesn’t match the condition speci-
fied by the RxParType field. See the earlier section 'Parity
Checking' for more information.

In HDLC/SDLC mode with the QAbort bit 1, the Receiver
sets this bit (along with RxBound) for a character that was
followed by an Abort sequence.

A channel can request an interrupt when software or a
DMA channel reads a character from the RDR that has this
bit set, if the Abort/PE IA bit in the Receive Interrupt Control
Register (RICR2) is 1. In this case software must write a 1
to Abort/PE to unlatch it and allow further interrupts; writing
a 0 to RCSR2 has no effect.

UM009402-0201