Zilog Z16C30 - Manual (Page 65)

4-16
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
4.10 THE /RXC AND /TXC PINS
Figure 4-1 shows each channel’s options for the function of
its /RxC and /TxC pins. The
RxCMode field in the Input/
Output Control Register (IOCR2-0) controls the function of
/RxC:
RxCMode Function of the /RxC pin
000 /RxC is an input
001 /RxC outputs RxCLK
010 /RxC outputs Rx Character Clock
011 /RxC outputs /RxSYNC
100 /RxC carries the BRG0 output
101 /RxC carries the BRG1 output
110 /RxC carries the CTR0 output
111 /RxC carries the DPLL Rx output
while the TxCMode field (IOCR5-3) controls the function of
the /TxC pin:
TxCMode Function of the /TxC pin
000 /TxC is an input
001 /TxC outputs TxCLK
010 /TxC outputs Tx Character Clock
011 /TxC outputs “Tx Complete”
100 /TxC carries the BRG0 output
101 /TxC carries the BRG1 output
110 /TxC carries the CTR1 output
111 /TxC carries the DPLL Tx output
Some of these possible outputs need further description.
A channel drives its Rx Character Clock high for one
RxCLK period as it transfers each character from the
Receive shift register to the Receive FIFO. Similarly, it
drives its Tx Character Clock high for one TxCLK period
each time it transfers a character from the Transmit FIFO to
the Transmit shift register. A channel’s /RxSYNC output
goes low for one RxCLK cycle each time its Receiver
recognizes a Sync or Flag sequence. The Tx Complete
output is suitable for controlling a driver on TxD. It is low
from the start of the first active bit of a sequence of one or
more consecutively-transmitted characters, through the
end of the last bit of the sequence. The BRG and CTR
outputs are square waves. The DPLL outputs were shown
earlier in this chapter.
While it’s not very useful to employ a high-speed free-
running clock as a source of interrupt events, for other uses
of /RxC and /TxC software can program a channel to
interrupt the host processor on either or both edges on
these pins, as described in the earlier section Edge Detec-
tion and Interrupts. Typically such interrupts would be
used for an input pin, that is, when RxCMode or TxCMode
is 00 or 01. Software should write a 1 to the
RxCDn IA or
TxCDn IA bit in the Status Interrupt Control Register
(SICR15 or SICR13) to make a channel detect falling
edges on /RxC or /TxC, and write a 1 to
RxCUp IA or
TxCUp IA (SICR14 or SICR13) to make it detect rising
edges.
As described in Edge Detection and Interrupts, the
RxCL/U or TxCL/U bit (MISR15 or MISR13) is 1 if the
channel has detected an enabled edge, until software
writes a 1 to the bit to clear it. The
/RxC or /TxC bit (MISR14
or MISR12) reflects the state of the pin transparently while
the L/U bit is 0, but is frozen while the L/U bit is 1. A 0 in
MISR14 or MISR12 indicates a high on the pin, and 1
indicates a low.
UM009402-0201