Zilog Z16C30 User Manual

Page 34

2-8

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

2.8.2 Bits and Fields in the BCR

(Continued)

16-Bit

(BCR2): this bit should be written as 1 when the host

data bus is 16 bits wide (or wider). Writing this bit as 0 has
two effects: it restricts the host to using byte transfers on
AD7-AD0 when reading and writing the USC’s registers,
and it makes the USC ignore the state of the “B//W” signal
or bit for register accesses. This bit also controls whether
“implicit” accesses to the CCAR, TDR, and RDR are 8 or
16-bit wide.

2PulseIACK

(Double-Pulse Interrupt Acknowledge; BCR1):

software should program this bit to 0 if the /PITACK pin isn’t
used or if it carries a single pulse when the host processor
acknowledges an interrupt, or to 1 if /PITACK carries two
pulses when the host processor acknowledges an inter-
rupt. (The latter mode is compatible with certain Intel
processors.)

SRightA

(Shift Right Addresses; BCR0): this bit is signifi-

cant only for a multiplexed bus — the USC ignores it for a
non-multiplexed bus. If SRightA is 1, the USC captures
register addressing from the AD6-AD0 pins and ignores
the AD7 pin. In this mode, AD0 carries the Upper/Lower

byte indication (U//L), AD5-AD1 carry the actual register
address, and AD6 carries the Byte/Word indication (B//W).
If SRightA is 0, the USC captures addressing from AD7-
AD1 and ignores AD0. It takes U//L from AD1, the register
address from AD6-AD2, and B//W from AD7. This bit has
no effect on the use of the S//D and D//C pins.

SRightA would be 0 when using the USC as an 8-bit
peripheral on a 16-bit bus, which isn’t likely to be a
common application. Some sections of this manual
assume that SRightA is 1.

All other bits in the BCR are reserved and should be
programmed as 0. If the processor can only write bytes to
the USC, software can only write the 8 LSBits of the BCR,
on the AD7-AD0 lines. In this case, the state of AD15-AD8,
when software writes the BCR, must be ensured by con-
necting these pins to pulldown resistors, or, if SepAd=1, to
host address lines.

2.9 REGISTER ADDRESSING

The flowchart of Figure 2-9 shows how the USC determines
which register to access when a host processor cycle
asserts /CS and one of /RD, /WR, or /DS.

In all register accesses, the A//B pin selects between the
two serial channels in the USC. The USC samples A//B,
and other pins as described below, at the rising/trailing
edge of /AS, or, if /AS is pulled up so that it’s always High,
at the falling/leading edge of /DS, /RD, or /WR.

2.9.1 Implicit Data Register Addressing

If the USC samples the D//C pin high, a write operation
accesses the Transmit Data Register (TDR) and a read
operation selects the Receive Data Register (RDR). The
access is implicitly 16 bits wide if the

16-bit

bit in the Bus

Configuration Register (BCR2) is 1 (indicating a 16-bit data
bus) or 8 bits wide if BCR2 is 0.

This means that, on a 16-bit bus, software can neither write
a byte to the TDR/TxFIFO nor read a byte from the
RDR/RxFIFO using an address that makes D//C high.
Instead, software must provide the explicit address of the
LS byte of the TDR/RDR, either directly or by writing it to the
CCAR.

2.9.2 Direct Register Addressing on
AD13-AD8

If the USC samples D//C low, and the SepAd bit in the Bus
Configuration Register (BCR15) is 1 (which should only be
the case with an 8-bit data bus) the USC samples the
AD13-AD9 pins as a

RegAd

to select which register to

access, and samples AD8 as U//L to select which byte of
the register to access. The USC always interprets a U//L bit
in the “little-Endian” fashion, with a 1 indicating the more-
significant 8 bits of the register.

If the USC samples AD13-AD8 as all zero in this mode,
indicating the Channel Command/Address Register
(CCAR), the USC uses the contents of the CCAR to select
which register to access, as described in ‘Indirect Register
Addressing’ below.

UM009402-0201