Zilog Z16C30 User Manual

Page 40

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Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

2.9.6 Serial Data Registers TDR and RDR

The RDR and TDR are actually “the read and write sides of”
the same register location. The USC ignores the state of
AD4, AD12, or CCAR4 (as applicable) whenever the rest
of the address indicates an access to TDR or RDR. For
simplicity Tables 2-1 and 2-2 show RDR at the lower
address and TDR at the higher one.

The MSBytes of RDR and TDR should never be read or
written alone, only as part of a 16-bit access. On a Zilog
16C0x or Motorola 680x0 system, use direct addresses 97
or 113 (61 or 71 hex) for channel B, and 225 or 241 (E1 or
F1 hex) for channel A, to select the LSByte for byte
transfers. On an Intel-based system, use the addresses
96, 112, 224, or 240 (60, 70, E0, F0 hex) correspondingly,
to select the LSByte for byte transfers.

2.9.7 Byte Ordering

Various microprocessors differ on the correspondence
between byte addresses and how bytes are arranged
within a 16- or 32-bit value. The Zilog Z80 and most Intel
processors use what’s sometimes called the “Little-Endian”
convention: the least significant byte of a word has the
smallest address, and the most significant byte has the
largest address.

The Zilog 16C0x and Motorola 680x0 processors are “Big-
Endian”: they store and fetch the MSByte in the lowest-
addressed byte, and the LSByte in the highest address.

Addressing of bytes within USC registers is inherently
"Little-Endian", such that the MSBytes of registers have
odd addresses.

For 16-bit serial data transfers only, two commands in the
RTCmd field of the Channel Command/Address Register
(CCAR15-11) allow the USC to be used with either kind of
processor. The “Select D15-8 First” and “Select D7-0 First”
commands control the byte ordering within a 16-bit trans-
fer of serial data, and apply to DMA and processor ac-
cesses to RDR and TDR.

2.9.8 Register Read and Write Cycles

Figures 2-10 through 2-13 show the waveforms of the
signals involved when the host processor reads or writes
a USC register. Separate drawings are included for the
signaling on a bus with multiplexed addresses and data,
and for a bus with separate address and data lines. On the
other hand, since waveforms get pretty boring after the first
few, several things have been done to minimize the num-
ber of figures.

The cases of separate read and write strobes, vs. a
direction line and a common data strobe, have been
combined by labelling the strobe traces as “/DS or
/RD” and “/DS or /WR”. The direction line R//W is shown
in the figures, but a note reminds the reader that its
state doesn’t matter with /RD and /WR.

The difference between “wait” and “acknowledge”
signaling is handled by showing the /WAIT//RDY trace
as “maybe or maybe not” going low, with appropriate
labelling. (The USC never asserts a “Wait” indication
during a register access cycle.)

Chapter 6 covers details of DMA cycles initiated by an
external DMA controller, while Chapter 7 covers interrupt
acknowledge cycles.

The actual timing parameters and electrical specifications
of the USC are given in the companion publication USC
Product Specification.

UM009402-0201