Zilog Z16C30 - Manual (Page 12)

Z16C30 USC ®
U SER ' S M ANUAL
viii
Z
ILOG
UM97USC0100
F
IGURE
T
ITLES
P
AGE
Chapter 7
Figure 7-1. An Interrupt Daisy Chain ........................................................................ 7-2
Figure 7-2. External Interrupt Control ........................................................................ 7-3
Figure 7-3. USC Interrupt Types & Sources ............................................................. 7-5
Figure 7-4. A Model of the Interrupt Logic for Source "s" and type "t" ...................... 7-7
Figure 7-5. An Interrupt Acknowledge Cycle Signaled by /SITACK, .............................
on a Multiplexed Bus ............................................................................ 7-10
Figure 7-6. An Interrupt Acknowledge Cycle Signaled by /SITACK, .............................
on a Non-Multiplexed Bus .................................................................... 7-11
Figure 7-7. A /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=0 ............. 7-12
Figure 7-8. A /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=1 ............. 7-13
Figure 7-9. The Receive Command/Status Register (RCSR) .................................. 7-15
Figure 7-10. The Receive Interrupt Control Register (RICR) .................................... 7-15
Figure 7-11. A Sample Service Routine for Receive Data Interrupts ........................ 7-17
Figure 7-12. The Transmit Command/Status Register (TCSR) ................................. 7-18
Figure 7-13. The Transmit Interrupt Control Register (TICR) .................................... 7-18
Figure 7-14. The Status Interrupt Control Register (SICR) ........................................ 7-19
Figure 7-15. The Miscellaneous Interrupt Status Register (MISR) ............................ 7-19
Figure 7-16. The Daisy-Chain Control Register (DCCR) ........................................... 7-22
Figure 7-17. The Interrupt Control Register (ICR) ..................................................... 7-22
Figure 7-18. The Interrupt Vector Register (IVR) ...................................................... 7-24
Chapter 8
Figure 8-1. Test Mode Data Register with TMCR 4-0=00101 (Clock Mux Outputs) ... 8-7
Figure 8-2. Test Mode Data Register with TMCR 4-0=00111 (Clock Mux Inputs) ...... 8-8
Figure 8-3. Test Mode Data Register with TMCR 4-0=01110 (I/O and Misc Status) .. 8-9
UM009402-0201