Zilog Z16C30 User Manual

Page 57

4-8

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

4.4 DATA FORMATS AND ENCODING

(Continued)

In NRZI-Mark mode, at the start of each bit cell the
transmitter inverts TxD for a 1 but leaves it unchanged for
a 0. In NRZI-Space mode, at the start of each bit cell the
transmitter inverts TxD for a 0 but leaves it unchanged for
a 1.

None of these NRZ-type modes, by itself, guarantees
transitions in the data stream. However, if the serial proto-
col can guarantee transitions often enough, then the DPLL
can use these transitions to recover a clock from the data
stream. By some method the protocol must eliminate long
bit sequences without transitions in the data: successive
zeroes for NRZ, NRZB, and NRZI-Mark and successive
ones for NRZ, NRZB, and NRZI-Space.

For example, NRZI-Space mode matches up well with
HDLC and SDLC protocols, because the Transmitter in-
serts a extra zero into the data stream whenever the
transmitted data would otherwise produce six ones in
succession. Thus, there is at least one transition every
seven bit times.

The reliability of clock recovery from any kind of NRZ data
stream depends on guaranteed transitions, on the
transmitter’s and receiver’s time bases being reasonably
similar/accurate, and on fairly low phase distortion in the

serial medium. Such schemes have the advantage that
bits can be sent at rates up to the maximum switching rate
(baud rate) of the medium.

The four Bi-phase modes, on the other hand, provide
highly reliable clock recovery and do not constrain the
content of the data, but they limit the data rate to half the
switching rate (baud rate) of the serial medium.

See the waveform for Bi-phase-Mark mode in Figure 4-4.
This encoding scheme is also known as FM1. The transmit-
ter always inverts the data at the start of each bit cell. At the
midpoint of the cell it changes the data again to indicate a
1-bit, but leaves the data unchanged for a zero. In Biphase-
Space mode (FM0) the transmitter always inverts the data
at the start of each bit cell. In the middle of the cell it
changes the data again for a zero-bit but leaves the data
unchanged for a one-bit. In Biphase-Level mode (also
called Manchester encoding), at the start of the bit cell the
transmitter makes TxD high for a one-bit and low for a zero.
It always inverts TxD in the middle of the cell. In Differential
Biphase Level mode, at the start of each bit cell the
transmitter inverts TxD for a zero but leaves it unchanged
for a one. It always inverts TxD in the middle of the cell.

4.5 MORE ABOUT THE DPLL

While the Transmitter and Receiver must be programmed
for the particular serial format to be used, the DPLL only
needs to know the general category of encoding on RxD,
in the

DPLLMode

field of the Hardware Configuration

DPLLMode

DPLL Operation/Decoding

DPLL disabled

Any NRZ mode

Biphase-Mark or -Space

Either Biphase-Level mode

In any of the NRZ modes, transitions on RxD occur only at
the boundaries between bit cells. The DPLL synthesizes a
clock having falling edges at bit cell boundaries and rising
edges in the middle of the cells. The Transmitter changes
TxD on falling edges of TxCLK and the Receiver samples
data on rising edges of RxCLK.

In the Bi-phase-Mark and Bi-phase-Space encodings,
there is always a transition at the boundaries between
active data bits, and there may or may not be a transition
at the center of each bit cell. The DPLL generates a receive
clock having its falling edge 1/4 of the way through the bit
cell, and its rising edge at the 3/4 point. The Receiver
determines each data bit from the state of RxD at rising
edges of RxCLK and checks for “missing clocks” around
falling edges. The DPLL generates a Transmit clock that is
the same as in NRZ modes. The Transmitter complements
the state of TxD at each falling edge of TxCLK, and may or
may not change TxD at rising edges, depending on the
current data bit. The DPLL produces clock transitions only
when it is "in sync" as described on the next page.

UM009402-0201