Zilog Z16C30 User Manual

Page 202

B-8

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

SERIAL & PROTOCOL QUESTIONS AND ANSWERS

(Continued)

The Transmit Control Block is being sent as data. What
am I doing wrong?

If the previous transmit frame ended normally, the TSB
is automatically routed to the proper registers in the
USC family. However, if you are starting up, or pro-

cessing a case where the previous frame did not
terminate normally (because of an underrun, for ex-
ample) it is necessary to condition the transmitter to
expect a TSB instead of data. The Load TCC com-
mand in the CCAR is the easiest way to do this. Refer
to the Technical Manual for more details.

DMA QUESTIONS AND ANSWERS

While in the master mode using the IUSC, what is the
timing of the Byte/Word signal?

B//W has the same timing as S//D and D//C. When the
IUSC is transferring a byte the signal is High; when the
IUSC is transferring a word the signal is Low.?

The IUSC Spec shows the Memory Read timing dia-
gram. If the DMA is in the middle of one of these cycles,
the memory is driving the data bus while /RD is low.
/RD will go high 25 nsec max after the falling edge of
CLK (param. 141). If the next DMA cycle begins on the
next rising CLK edge, then the DMA will come out of tri-
state and drive the bus with the address 25 nsec max
after the rising edge of CLK. With a 16 MHz DMA clock,
about 30 nsec of CLK-low time exists. Going strictly
from the numbers given, param 141 could be 25 nsec
exactly, while param 148 could be close to zero nsec.
This would give the memory only about 5 nsec in which
to go tri-state before the DMA began driving the bus
with the address (30 nsec CLK-low time minus 25 nsec
for /RD to go high plus 0 nsec possible for the DMA to
begin driving the bus after CLK goes high).

Can you provide a more realistic number to use
(/RD-high to-ADbus-being-driven)? Is the next cycle
really going to begin at the last rising edge (i.e., is the
last rising CLK edge the same as the first rising CLK
edge shown on the page)?

Yes, the next rising edge of CLK will start another DMA
cycle. However, parameter #145 has been modified to
also carry a minimum value. This is because on a
single chip one cannot have one delay time that is at
the maximum while another delay time is at the mini-
mum; the two numbers will track. This gives the de-
signer much more than the 5 ns that you cite above

Is there a mode where the USC can deassert the
/DMAREQ pin without using the /DMAACK (that is,
/TxACK & /RxACK)?

This is just a flow through DMA transfer, which is
supported by the USC. The DMA controller performs
two bus cycles for each piece of data transferred
between the USC and memory. The first cycle reads
data from the source, be it the USC or the memory. The
DMA controller captures this read data and then
presents it on the data bus again in the second cycle
which is a write to memory if the data came from the
USC or a write to the USC if the data came from
memory. The main advantage of flowthrough transfers
is that they involve minimal hardware design consider-
ations, because both cycles of each pair are similar to
bus cycles performed by the host processor. The
/RXREQ and /TxREQ signals will be deasserted dur-
ing the bus cycle just as if /RxACK or /TxACK were
being used to transfer the data. The /TxACK and
/RxACK pins can be used as outputs or as polled
inputs in this case.

What’s the largest memory buffer possible when using
the array or linked list mode in the IUSC? In which
register is it programmed?

The length of the buffer is programmed in the relevant
Byte Count Register. Since these registers are 16-bits
wide, there is a 64K byte limit on the size of buffers.

When using the IUSC, what is the minimum time
between /BUSREQ active and /BIN active?

There is no particular timing requirement or relation-
ship between /BUSREQ and /BIN. The IUSC is always
ready to deal with a falling edge on /BIN. If it is
requesting the bus, it keeps /BUSREQ asserted while
it uses the bus, which lasts until it doesn’t have any-
thing more to do, or its usage is limited by the BDCR,
or /BIN goes high or /ABORT goes low. If it doesn’t
want to use the bus it drives /BOUT low for as long as
/BIN stays low.

UM009402-0201