Zilog Z16C30 - Manual (Page 23)

1-10
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z
ILOG
Table 1-6. Interrupt Features of the USC
Interrupt Acknowledge
Daisy Chaining
was one of Zilog’s original contributions to microprocessor architecture. On the USC
its use (to determine which of several interrupting devices to service first) is optional,
and performance is much improved compared to older devices.
External Interrupt Control can be used instead of a daisy chain to implement interrupt priority schemes other
than strict priority, such as “fairness”, rotating, or first-come first-served.
Types of interrupts that can be selectively enabled or disabled include Receive Status,
Receive Data, Transmit Status, Transmit Data, I/O Pin, and Miscellaneous.
Receive Status Interrupt sources that can be selectively armed or disarmed include Exited Hunt, Idle
Received, Break, Abort (immediate and/or synchronized to received data), End of
Frame/Message, Parity Error, and RxFIFO Overrun.
Receive Data Interrupt can occur when the RxFIFO reaches a programmed level of fullness.
Transmit Status Interrupt sources that can be selectively armed or disarmed include Preamble Sent, Idle
Sent, Abort Sent, End of Frame/Message Sent, CRC Sent, and Tx Underrun.
Transmit Data Interrupt can occur when the TxFIFO reaches a programmed level of emptiness.
I/O Pin Interrupt sources that can be selectively armed or disarmed include rising and/or falling
edges on the /DCD, /CTS, /RxREQ, /TxREQ, /RxC, and /TxC pins.
Miscellaneous Interrupt sources that can be selectively armed or disarmed include Rx Character Counter
Underflow, DPLL Sync Loss, Baud Rate Generator 0 zero, and BRG1=0.
Nested Interrupts are fully supported in that the USC includes an Interrupt Pending and Interrupt
Under Service bit for each type of interrupt.
Interrupt Acknowledge Cycles The USC is compatible with a wide variety of processors in that the signal that
identifies an acknowledge cycle can be sampled like an address bit, or can carry
a single or double pulse similar to a read or write strobe.
Interrupt Vectors The USC can include identification of the highest priority requesting type of interrupt
in the vector that it returns during an interrupt acknowledge cycle.
Non-Acknowledging Buses Software can simulate the effects of interrupt acknowledge cycles if the USC is used
on a bus that doesn’t provide such cycles, like the ISA (AT) bus.
UM009402-0201