Zilog Z16C30 - Manual (Page 84)

5-17
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
As in other synchronous modes, the MSBit of the
TxSubMode field (CMR15) controls whether the Transmit-
ter sends its accumulated CRC code if a Transmit Underrun
condition occurs.
On the receive side, external logic should monitor the link
and drive the /DCD pin low when it detects carrier. Figure
5-7 shows the relationship between an Ethernet frame on
RxD and the signal on /DCD. Besides the auto-enable
already noted for RMR1-0, software should program the
DCDMode field of the Input/Output Control Register
(IOCR13-12) as 01 to select the mode of the /DCD pin.
After /DCD goes low, the Receiver hardware hunts for 58
alternating bits of preamble, with the final 0 changed to a
1 as a “start bit”. When it finds this sequence it starts
assembling data and may check the Destination Address
in the frame as described below.
After a frame, the external hardware should drive /DCD
high so that it sets up to the rising RxCLK edge after the one
at which it samples the last bit of the CRC. In this mode and
External Sync mode only among synchronous modes, if
/DCD goes high while the Receiver is in the midst of
assembling a character, it continues on to sample the
remaining bits of the character and place the character in
the RxFIFO.
The receiver marks the character that was partially or
completely assembled when /DCD went high with RxBound
status in the RxFIFO. As described in later sections, this
marking may set the channel’s Received Data Interrupt
Pending bit and thus force an interrupt request on its /INT
pin, and/or it may force a DMA request on the /RxREQ pin.
The LSBit of the RxSubMode field (CMR4) controls whether
the Receiver checks an Address field at the start of each
frame. If CMR4 is 0, the Receiver places all received
frames in the RxFIFO and leaves address-checking to the
software. (Some contexts call this “promiscuous mode”.) If
CMR4 is 1, the Receiver compares the first two characters
(16 bits) of each frame to the contents of the Receive Sync
Register (RSR). It compares RSR0 to the first bit received,
and RSR15 to the last bit, regardless of any “Select Serial
Data MSB First” commands that the software may have
written to the RTCmd field (CCAR15-11). The Receiver
ignores the frame unless the address matches, or unless
the first 16 bits are all ones, which indicates a frame that
should be received by all stations. The Receiver places the
address in the RxFIFO so that the software can differenti-
ate “locally addressed” frames from “global” ones.
Except in the CRC, characters (“octets”) are sent LSBit
first. The Length field that follows the Destination and
Source Address fields is sent MSByte-first. IEEE 802.3
doesn’t include any other byte ordering information.
The USC doesn’t use the three LSBits of the TxSubMode
field (CMR14-12) in 802.3 mode, nor the three MSBits of
RxSubMode (CMR7-5), but Zilog reserves these bits for
future enhancements. Software should always program
them with zeroes in this mode.
UM009402-0201