Zilog Z16C30 User Manual

Page 207

B-13

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

The IUSC Technical Manual states that /DS and
/INTACK should never be active at the same time.
However, the nonmultiplexed Interrupt Acknowledge
Cycle timing diagram shows both of these pins active
at the same time.

The manual states that no two strobe signals should be
active at the same time. In the case of Status Interrupt
Acknowledge cycles, the /INTACK pin is a status
signal and the /DS pin is the signal that strobes the
interrupt vector. This is different from the case of the
Pulsed or Double-Pulsed Interrupt Acknowledge cycle
where the /INTACK pin is strobing in the interrupt
vector.

Explain why sometimes the reading on the fill level of
the receive FIFO reports that there are 33 bytes in a 32
byte deep FIFO?

When the receive FIFO is overrun, it can read that there
are 33 bytes available. This is due to the fact that there
is a holding register where data is held before being
put into the receive FIFO (this allows status like RxBound
to be marked with the data when it loaded to the FIFO).
When the receiver overruns it stops receiving data.
When the last byte of data is transferred to memory, a
Rx Status interrupt is generated (the interrupt is trig-
gered by removing the byte with overrun status). The
Rx FIFO Purge command is necessary to clear the
overrun and re-enable receiving data. It may be desir-
able to also issue the command “Enter Hunt Mode” (in
the RCSR register) so that reception starts at the
beginning of the next frame.

When the IUSC is operating in Linked List mode with
Early Buffer Termination and the End Of Buffer (EOB)
is reached somewhere in the last buffer, what is the
sequence of setting EOB and EOL? Does the EOL bit
get set at the same time as the EOB bit, or will the EOB
become set first, and the EOL become set second
after the DMA tries to fetch the next link?

The EOB bit is set during the clock cycle between the
last buffer access and the first array fetch. The EOL bit
is set during the clock cycles immediately after the
array fetch which reads the zeros in the buffer length
field, indicating no more buffers. Under normal cir-
cumstances the CPU servicing the EOB interrupt will
see both of the bits set at the same time, but if the DMA
releases the bus before fetching the array entry, and
the CPU is able to read the status bits during this time,
only the EOB bit will be set.

If multiple interrupts occur, how many can the IUSC
queue up?

There are 30 interrupt sources in the IUSC, divided into
six types in the Serial section and eight DMA interrupt
sources (4 of each type per channel). Each source is
individually maskable; those that are armed and en-
abled are ORed together to assert the single /INT pin.
When the CPU acknowledges the interrupt, the IUSC
tells the CPU which is the highest priority type that is
enabled and requesting. If all 8 types were requesting,
I suppose you could say that the lower 7 types were in
some sense queued. For some of the sources that
involve edge detection, such as the modem control
pins, there’s a more meaningful answer. As noted in
the “Edge Detection and Interrupts” section of IUSC
Technical Manual, there is a hidden edge detection
latch that can record another edge of the same polarity
before software has finished handling the previous
edge of that type. So for these sources the answer is
“the IUSC can queue a second interrupt for some
sources, besides the one it’s requesting for”.

When should the Sent bits (i.e. EOF/EOM Sent, CRC
Sent, All Sent) in the TCSR be reset during an interrupt
service routine?

As stated in the IUSC Technical Manual, software
should clear or unlatch status register bits after clear-
ing IP and before clearing and rearming the IA bits.

UM009402-0201