Zilog Z16C30 - Manual (Page 6)

Z16C30 USC ®
U SER ' S M ANUAL
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Z
ILOG
UM97USC0100
C
HAPTER
T
ITLE AND
S
UBSECTIONS
P
AGE
Chapter 3 A Sample Introduction
3.1 Introduction ....................................................................................................... 3-1
Chapter 4 Serial Interfacing
4.1 Introduction ....................................................................................................... 4-1
4.2 Serial Interface Pin Descriptions ....................................................................... 4-1
4.3 Transmit and Receive Clocking ........................................................................ 4-2
4.3.1 CTR0 and CTR1 ...................................................................................... 4-2
4.3.2 The Baud Rate Generators ..................................................................... 4-2
4.3.3 Introduction to the DPLL ......................................................................... 4-5
4.3.4 TxCLK and RxCLK Selection .................................................................. 4-5
4.3.5 Clocking for Asynchronous Mode .......................................................... 4-6
4.3.6 Synchronous Clocking ............................................................................ 4-6
4.3.7 Stopping the Clocks ............................................................................... 4-6
4.4 Data Formats and Encoding ............................................................................. 4-7
4.5 More About the DPLL ........................................................................................ 4-8
4.6 The RxD and TxD Pins .................................................................................... 4-10
4.7 Edge Detection and Interrupts ........................................................................ 4-11
4.8 The /DCD Pin ................................................................................................... 4-13
4.9 The /CTS Pin .................................................................................................... 4-15
4.10 The /RxC and /TxC Pins .................................................................................. 4-16
4.11 The /RxReq and /TxReq Pins .......................................................................... 4-17
4.12 The /RxACK and /TxACK Pins ......................................................................... 4-17
Chapter 5 Serial Modes and Protocols
5.1 Introduction ....................................................................................................... 5-1
5.2 Asynchronous Modes ........................................................................................ 5-1
5.3 Character Oriented Synchronous Modes .......................................................... 5-3
5.4 Bit Oriented Synchronous Modes ..................................................................... 5-4
5.5 The Mode Registers (CMR,TMR & RMR) .......................................................... 5-5
5.5.1 Enabling and Disabling the Receiver and Transmitter ........................... 5-7
5.5.2 Character Length .................................................................................... 5-7
5.5.3 Parity, CRC, Serial Encoding .................................................................. 5-8
5.6 Asynchronous Mode ......................................................................................... 5-9
5.6.1 Break Conditions .................................................................................. 5-10
5.7 Isochronous Mode ........................................................................................... 5-10
5.8 Nine-Bit Mode .................................................................................................. 5-11
5.9 External Sync Mode ........................................................................................ 5-12
5.10 Monosync and Bisync Modes ......................................................................... 5-12
5.11 Transparent Bisync Mode ............................................................................... 5-14
5.12 Slaved Monosync Mode .................................................................................. 5-15
5.13 IEEE 802.3 (Ethernet) Mode ............................................................................ 5-16
5.14 HDLC/SDLC Mode .......................................................................................... 5-18
5.14.1 Received Address and Control Field Handling .................................... 5-18
5.14.2 Frame Length Residuals ....................................................................... 5-20
5.14.3 Handling a Received Abort .................................................................. 5-20
UM009402-0201