Zilog Z16C30 - Manual (Page 120)

6-1
Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
6.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
6
D IRECT M EMORY A CCESS (DMA)
I NTERFACING
Chapter 5 described many of the features of the USC ® that
support handling serial traffic via DMA, that is, without
processor intervention on a byte-by-byte basis. This chap-
ter describes how to interface external DMA controllers
and how to program the USC to work with them.
DMA and processor data transfers can be mixed in several
ways. The USC’s two Receivers and two Transmitters can
be handled via any mixture of DMA and programmed
transfers. Furthermore, software can even mix DMA and
programmed transfers for a particular Receiver or Trans-
mitter.
For example, software could use the Wait4RxTrig bit
(CCR13) to inhibit DMA transfers at the start of each
received frame, so that it can read the first few characters
of the frame from the RxFIFO itself. The software can then
determine the kind of frame from examining those first
characters, optionally program the receive DMA controller
accordingly, and then write the “Trigger Rx DMA” com-
mand to the RTCmd field of the Channel Command/
Address Register (CCAR15-11). The DMA controller can
then transfer the rest of the frame into memory without
further software intervention.
6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION
DMA controllers can operate in one of two ways that are
called “flyby” or single-cycle mode and “flowthrough” or
two-cycle mode. Figures 6-1 and 6-2 illustrate flowthrough
mode, in which the DMA controller performs two bus
cycles for each piece of data transferred between the
peripheral device and memory. The first cycle reads data
from the source, be it the peripheral or the memory. The
DMA controller captures this read data and then presents
it on the data bus again in the second cycle, which is a write
to memory if the data came from the device, or a write to the
device if the data came from memory. The main advantage of flowthrough transfers is that they
involve minimal hardware design considerations, because
both cycles of each pair are similar to bus cycles per-
formed by the host processor. In the case of the USC
there’s a secondary advantage in that the /TxACK and/or
/RxACK pin(s) can be used for general-purpose input or
output.
UM009402-0201