Zilog Z16C30 - Manual (Page 203)

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Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
Q: When the DMA in the IUSC reads external memory for
array or linked-list table information, does it attempt to
fetch all bytes in one burst access or does it release the
bus between byte/word accesses?
A: The IUSC will attempt to move all the bytes in one
access. Of course, if the transfer is interrupted or
aborted, subsequent transfers will be required.
Q: In the IUSC in array and linked-list modes and in the
event of a receive CRC error, is the current receive
buffer reused?
A: No, buffers are not re-used when a CRC or any other
error is detected. A buffer is only re-used when its
address is explicitly given to the DMA a second time.
Q: When using array or linked list modes in the IUSC, can
several chained data buffers be sent in one frame, or
is CRC and closing Flag sent at the end of each buffer?
A: Yes, multiple memory buffers can be sent in one frame.
The IUSC provides features which allow the data
buffer boundaries to be independent of serial data
packet boundaries. The IUSC uses separate counters
for the size of the memory buffer and the size of the
frame (TCLR). The best way to use the TCLR is to use
the Transmit Control Block (TCB) feature (CCR bits
D15 & D14). By putting the size of the packet in
memory in the TCB, the frame length value will auto-
matically go to the Transmit Count Limit Register
(TCLR) and will cause the CRC and Flag to be ap-
pended after this number of bytes has been transmit-
ted, independent of DMA buffer boundaries.
Q: When does the IUSC release the bus relative to
/BUSREQ going inactive?
A: /BUSREQ is driven high from the same rising edge on
CLK at which it releases the various other bus signals.
This is shown in the IUSC Technical Manual under
“Bus Acquisition and Release Timing”.
Q: What is the function of the S//D and D//C pins when the
IUSC is bus master?
A: The S//D and D//C pins can be configured to output the
type of DMA access that is in progress. If these pins
are configured as inputs only, they are ignored during
the DMA transfers and the system should always drive
them.
Q: When using Receive Status Block with 16-bit DMA
transfers and a odd number of data bytes is received,
will the status block be transferred to memory on odd
or even memory addresses?
A: The data transfer which moves the last byte of data is
still a word transfer of which only one byte is valid.
Therefore, the status block (or next data) will be to an
even addresses.
Q: Can an IUSC DMA channel that was terminated by
/ABORT or /BIN going active or inactive, respectively,
resume transfers where it stopped?
A: If the DMA transfer is stopped by negation of /BIN, the
IUSC will assert /BUSREQ again automatically, as
soon as 8 or 40 clocks have gone by per MinOff39
(DCR5). Then when the processor or arbiter answers
with /BIN the DMA will start up exactly where it left off.
If the DMA transfer is stopped by the assertion of
/ABORT, the BUSY bit is cleared, so the DMA channel
won’t do anything again until the software sets it again
by means of one of the Start commands. Software
controls whether this restart is “in place” (Start or Start/
Continue), or whether it drops back to the start of a
memory buffer (Start/Init).
Q: In HDLC mode using DMA, can the USC notify the CPU
when a closing flag is encountered by the receiver
before the fill level is reached by using a pin?
A: When programmed as a DMA request, the /RxREQ pin
goes normally active when the FIFO reaches the fill
level. This function is enabled by setting the CCAR
(D15-D11) for “receive DMA request.” The
/RxREQ signal will also go active when the receiver
writes the last byte before the closing Flag of a re-
ceived message into the Rx FIFO.
Q: Why is DMA transmit request, /TxREQ, asserted be-
fore the transmitter is enabled?
A: The DMA request signals are independent of the
transmit and receive logic. Therefore, if the transmit
FIFO is below the programmed fill level, /TxREQ will go
active independent of the transmitter being enabled.
This is typical when first starting up a channel since the
FIFO is empty when /TxReq is enabled.
Q: When using the IUSC on a 16-bit bus, how is the last
byte transferred to memory if the there are an odd
number of bytes in the received message? Is there a
mechanism to handle this?
A: In serial protocols which result in the IUSC setting the
RxBound bit in the RCSR (HDLC, 802.3, 1553B, NBIP,
External Sync, Transparent Bisync) the byte with
RxBound status set will be transferred to memory
regardless of its byte/word boundary in the received
message. The Rx DMA will continue to request trans-
fers until the character with RxBound status is moved
to memory. When only one byte remains in the Rx
FIFO, the Rx DMA will complete a 16-bit transfer to
memory. The fact that only one byte of the transfer is
valid is indicated by the 1stBE (RCSR14), or by the odd
value of the Receive Character Count (RCC).
UM009402-0201