Zilog Z16C30 - Manual (Page 153)

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Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
7.16.3 Handling a Type
The process of handling a single type of interrupt is the
same regardless of whether the overall ISR handles only
the highest priority pending type, or all the pending types
within the device. The necessary steps vary for the various
types in the USC.
The following descriptions don’t attempt to cover every-
thing that each type of ISR should do, only the minimum
requirements needed to keep the interrupt subsystem
operating correctly.
Receive Status or Transmit Status Type
1.
Write the DCCR to clear the IP bit.
2. Read the RCSR or TCSR and handle the indicated
conditions appropriately.
3. After all the conditions have been handled, write a byte
to the LSbyte of the RCSR or TCSR, that has a 1 for
each status bit that was handled and is armed by a 1
in the corresponding IA bit in the RICR or TICR. This
clears/unlatches these status bits.
4. Write a zero byte to the LSbyte of the RICR or TICR,
which disarms all the sources/status bits.
5. Write a byte to the same LSbyte, to re-arm those
sources/status bits that should be armed for the future.
Steps 4 and 5 are needed only for these two types, to
ensure that another interrupt will occur if the hardware sets
armed sources/status bits after step 2, or if the bits are
otherwise left as 1 by the ISR.
I/O Pin or Miscellaneous Type
1.
Write the DCCR to clear the IP bit.
2. Read the MISR and handle the indicated conditions
appropriately.
3. After all the conditions have been handled, write a byte
to the LSbyte of the MISR, that has a 1 in each “L/U” bit
that was handled and is armed by a 1 in the corre-
sponding IA bit in the SICR. This clears/unlatches
these status bits. (Of course, software may want to
write ones to other L/U bits as well, such as those for
unarmed conditions.)
Receive Data Type
1.
Write the DCCR to clear the IP bit.
2. Read the RDR often enough to bring the fill level below
the “Rx Data Interrupt Request Level” in the RICR.
Under some conditions, writing a Purge Rx FIFO
command to the CCAR would eliminate the need to
read the TDR.
Typically, the ISR wants to read the fill level from the RICR,
and read the RDR the number of times indicated by that
value. In HDLC and similar modes, because the “RD”
interrupt occurs for the end of a frame as well as when the
fill level reaches the Request Level, software can’t blindly
read the number of characters set by the Request Level.
On a 16-bit bus the minimum Request Level is 01 (meaning
interrupt when 2 characters have been received). In such
a system it’s OK for software to read only pairs of charac-
ters and leave the last (unpaired) character to be handled
on the next interrupt. The exception is that in HDLC and
similar modes, if the ISR gets a fill level of 01 from its first
read of the RICR, the available character must be the last
one of a frame, and as such should be read individually.
If the Request level is low and the serial rate is high, it might
happen that enough characters arrive while software is
reading the number indicated by the initial read from the
RICR, so that the number of characters in the RxFIFO never
falls below the Request Level. This is particularly possible
if the Request Level is 01 (meaning interrupt when 2 empty
slots) and software only reads character pairs from the
RDR. If this can happen, after software finishes reading
each block of data, it should read the RICR again, and read
more data from the RDR if needed, to ensure that future Rx
Data interrupts will occur.
In HDLC and similar modes, software will want to know
where frames end. On a 16-bit bus, if the oldest character
in the RxFIFO is the last one of a frame, and software tries
to read 2 characters from the RDR, the USC only removes
the oldest character from the RxFIFO. The routine handling
Receive Data interrupts can determine frame/message
boundaries in two ways:
a. Read the RCSR after each read from the RDR. If the
1stBE or 2ndBE bit and the RxBound bit are set, the
previous read included the last character of a frame.
In this case, if 1stBE is 1 then the last read yielded only
1 character, else it included 2 characters.
b. Enable nested interrupts and have the Rx Status ISR,
when it sees an RxBound condition, do something to
affect the operation of the RxData ISR when it resumes.
This is tricky but is the sort of thing that can help make
life as a programmer interesting.
UM009402-0201