Zilog Z16C30 User Manual

Page 35

2-9

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

Whenever it uses CCAR as an indirect address, the USC
thereafter clears CCAR6-0 to zero, so that the next access
to CCAR address again references all 16 bits of the CCAR
itself. Thus, after writing a register address to the CCAR,
reading or writing the CCAR address accesses the regis-
ter selected by the address written, but another write to the
CCAR address thereafter again writes an address into the
CCAR.

CCAR can always be used to select a register for a
subsequent access to the CCAR address, even if the USC
detected activity on /AS after Reset, and regardless of the
state of SepAd (BCR15).

Typically when software uses indirect register addressing,
the CCAR address is the only one it reads and writes, every
other access being to write a register address. Note that
the CCAR itself can be accessed in a single read or write
operation: for example, on a 16-bit bus to write a command
to the RTCmd field, software doesn’t have to first write the
address of the CCAR (which is zero). Specifying a register
address for the next access to the CCAR can be done in
the same write operation with issuing a command in
RTCmd and/or changing the RTMode field.

‘The RxD and TxD Pins’ in Chapter 4 describes how the

RTMode

field in the CCAR controls echoing and looping

between the Transmitter and Receiver. Typically this field
is zero, but in applications using indirect register address-
ing and non-zero RTMode values, software must take care
to preserve the current value of RTMode when it writes
register addresses to the CCAR.

When using indirect addressing, some hardware/software
mechanism has to prevent a USC interrupt, or any interrupt
that leads to a context switch away from an interrupted
USC task, from occurring between the time an address is
written into the CCAR and when the subsequent read or
write is done. This is because an address that has been
written into the CCAR is part of the interrupted task’s
context that would want to be saved, but there’s no way to
read such an address out of the USC — reading the CCAR
returns the contents of the addressed register.

2.9.3 Direct Register Addressing on
AD6-AD0/AD7-AD1

If the USC samples D//C low, SepAd (BCR15) is 0, and the
USC detected activity on /AS before or as the BCR was
written, the USC samples the low-order AD pins to deter-
mine which register to access. It takes the register selec-
tion (RegAd) from AD5-1 if SRightA (BCR0) is 1, or from
AD6-AD2 if SRightA is 0. If 16-bit (BCR2) is 1, the USC
samples AD6 (or AD7 if SRightA/BCR0 is 0) as B//W to
determine whether to access all 16 bits if the register (if B/
/W is 0) or just 8. If 16-bit is 0 or B//W is 1, it samples AD0
(or AD1 if SRightA is 0) as U//L to select which byte of the
register to access. The USC always interprets a U//L bit in
the “little-Endian” fashion, with a 1 indicating the more-
significant 8 bits of the register. U//L should be 0 for all 16-
bit accesses.

If the USC samples AD6-0 (or 7-1 if SRightA is 1) as all zero
in this mode, indicating the Channel Command/Address
Register (CCAR), the USC uses the contents of the CCAR
to select which register to access, as described in the next
section.

2.9.4 Indirect Register Addressing in the
CCAR

If the USC samples D//C low, and:

SepAd (BCR15) is 1 and the USC samples AD13-AD8
as all zero indicating the CCAR, or

SepAd is 0, the USC detected activity on /AS before or
as the BCR was written, and it samples AD6-AD0 as all
zero indicating the CCAR, or

SepAd is 0 and the USC did not detect activity on /AS
before nor as the BCR was written,

then it uses the less-significant byte of the CCAR to select
which register to access.

Figure 2-8 shows the CCAR. When the USC takes indirect
register addressing from it, the RegAd field (CCAR5-1)
selects which register to access. If 16-bit (BCR2) is 1, the
USC uses CCAR6 as B//W to determine whether to access
all 16 bits of the register (if B//W is 0) or just 8. If 16-bit is 0
or B//W is 1, it uses CCAR0 as U//L to select which byte of
the register to access.

The USC always interprets a U//L bit in the “little-Endian”
fashion, with a 1 indicating the more-significant 8 bits of the
register. U//L should be 0 for all 16-bit accesses.

UM009402-0201