Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 198)

Catalyst Enterprises Inc. TA700/800 SPECIFICATIONS
184
Master Mode
Read/Write to I/O, MEM or configuration registers.
DMA transfers of up to 128K, real-time.
Single execution, loop up to 65535 or indefinite.
Insert user defined Wait states, unlimited, any location.
Force Interrupts, Errors, Parity Errors.
Perform special bus cycles.
Test memory blocks.
Read Modify Write memory.
Execute programs with or without GNT# from arbiter.
Several programs may be cascaded for on-the-fly execution.
Respond to Retry, Abort and Disconnect.
Perform Dual address cycle programs.
Split completion for PCI-X exerciser.
Target Mode
Termination Type Transfer data, Retry, Disconnect with or without data, Abort with or
without data.
Decode Address User defined I/O, Memory Read, Write single address or range, special
cycle etc.
DEVSEL Speed Fast (Not available in current version), Medium, Slow, Subtractive or
Below Subtractive.
Split response for PCI-X exerciser.
Local Memory
Read/Write memory 1 Meg Byte memory on board for random access read/write operation
Memory Depth 1MB organized as 8 x 128 Kbyte locations.
Transactions 32/64 bit
DEVSEL Speed Assertion Slow
Initial Latency
7 wait states.
Not available for PCI-X and TA800, in current version of software.