Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 170)

Catalyst Enterprises, Inc. Special Setups
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Table 3. PCI Protocol Errors (0-51)
Err.# Description
ERR0 FRAME# must be de-asserted as soon as IRDY# can be asserted from the time STOP# was asserted PCI Rev 2.2-
3.3.3.2.1.Rule 5
ERR1 Back-to-Back timing was used in a transaction in which was not proceeded by a write transaction form the same master.
PCI Rev 2.2 -3.4.2
ERR2 FRAME# is not asserted within 16 clocks from the time GNT# was asserted. PCI Rev 2.2 - 3.4.1
ERR3 FRAME# was asserted before the bus was granted(before GNT# was asserted).PCI Rev 2.2 -3.4.1
ERR4 IRDY# was not asserted a cycle immediately after FRAME# was deasserted. PCI Rev 2.2 - 3.3.1
ERR5 Improper termination .Either IRDY#, TRDY#, or STOP# were not deasserted after FRAME# was deasserted.PCI Rev
2.2 - 3.3.1
ERR6 IRDY# was asserted on the same clock edge that FRAME# was asserted .PCI Rev 2.2 - 3.3.1
ERR7 IRDY# was asserted when FRAME# was high.PCI Rev 2.2 - Appendix C,Rule 7
ERR8 After IRDY# was asserted, IRDY# or FRAME# were changed before the current data phase was completed or
FRAME# reasserted during the same transaction. PCI Rev 2.2 - Appendix C, Rules 8 b and 8 d
ERR9 (*Not implemented*)"IRDY# was asserted during the second address phase of a Dual Address Cycle. PCI Rev 2.2 -
3.9"
ERR10 PERR# was asserted during special cycle. PCI Rev 2.2. - 3.7.4.1
ERR11 PERR# was asserted during address cycle. PCI Rev 2.2. - 3.7.4.2
ERR12 (*Not implemented*) PAR does not match parity across AD[31:0] and CBE[3:0] PCI Rev 2.2 - 3.7.1
ERR13 (*Not implemented*) PAR64 does not match parity across AD[63:32] and CBE[7:4] Rev 2.2 - 3.8
ERR14 (*Not implemented*) Data parity error was detected on AD[31..0], but PERR# was not asserted. PCI Rev 2.2 -
Appendix C. Rule 32.b
ERR15 (*Not implemented*) Data parity error was detected on AD[63..32], but PERR# was not asserted. PCI Rev 2.2 -
Appendix C, Rule 37 c
ERR16 "DEVSEL# was removed while transaction was not completed yet. PCI Rev 2.2 - 3.3
ERR17 Target has responded to a reserved command by asserting DEVSEL#. PCI Rev 2.2 - 3.1.1
ERR18 DEVSEL# was asserted during special cycle. PCI Rev 2.2. - 3.6.2
ERR19 DEVSEL# was asserted before FRAME# was asserted. PCI Rev 2.2. - 3.3.1 and 3.3.2
ERR20 Target does not allow for turnaround time. TRDY# must not go low at the first clock after assertion of FRAME# in a
read transaction. PCI Rev 2.2 - 3.3.1. & 3.3.2.
ERR21 TRDY# was asserted before DEVSEL# was asserted. PCI Rev 2.2 - Appendix C, Rule 14
ERR22 DEVSEL#, TRDY# or STOP# were changed before the current data phase was completed, after TRDY# was asserted.
PCI Rev 2.2 - Appendix C, Rule 12 d
ERR23 TRDY# asserted while target is requesting abort. PCI Rev 2.1. - 3.3.3.2.1.