Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 193)

TA700/800 SPECIFICATIONS Catalyst Enterprises, Inc.
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TA700/800 SPECIFICATIONS
ANALYZER
Bus Type
TA700/800 PCI / PCI-X
TA700C CPCI
TA700PDC PMC
Bus width 32 or 64 bit wide
Maximum Clock Rate Up to 100 MHz (Up to 66.66 MHz for PMC, up to 133.33 MHz for
TA800) analyzer
Up to 66.66 MHz (Up to 133.33 MHz for TA800) exerciser
Min 25 MHz (PCI, PCI-X, CPCI)
100 kHz (PMC, TA800)
External Signals
16 Input Channels Sampled in memory, may be used as trigger
inputs or as input to performance analysis. (Not
supported by TA800)
1 External Trigger Out Positive or negative TTL Level synchronized to
the sequencer first time trigger.
Memory Depth per Channel
Trace, 95 PCI signals 128K
Trace, optional
4 Meg (Not supported for TA700PDC or TA800)
External Signals 16 x 128K
Exerciser, 95 signals 128K
Protocol Errors 128K
Timing Errors 128K
Time Tag 128K
Word Recognizers 8 Event patterns.
Triggering Events Any of the 8 events, Boolean equation of the events, or trigger on timing
or protocol errors.
30 - 20 bit Counters Used as 30 event or delay counters at each state. (14 - 20 bit counters in
TA800 used as 14 event or delay counters at each state)
32 Level Sequencer Supported at each level by Store, Set Trigger, Set Tag, Discard, If, Else If,
GoTo, Delay Time, Delay Count and Start Exerciser statements.(16 level
sequencer for TA800)