Teledyne LeCroy TA700_800_850 User Manual - Manual (Page 173)

Special Setups Catalyst Enterprises, Inc.
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PCI-X Protocol Errors
Table 4. PCI-X Protocol Errors (0-58)
Err. # Description
ERR0 Burst transactions are only allowed for memory transactions or Split Completion. PCI-X Rev 1.0 -1.5
ERR1 The starting address of Configuration Read and Configuration Write transactions must be aligned to a DWORD
boundary. PCI-X Rev 1.0 -1.10.1
ERR2 The C/BE bus is reserved and must be driven high the clock after the attribute phase. PCI-X Rev 1.0 -1.10.1
ERR3 The initiator must assert FRAME six clocks after GNT is asserted and the bus is idle on a configuration
transaction. PCI-X Rev 1.0 -1.10.2
ERR4 IRDY must be asserted two clocks after attribute phase. PCI-X Rev 1.0 -1.10.2
ERR5 (*Not implemented*) For write and split completion initiator must toggle between first and last data in starting
wait states
ERR6 Fast back-to-back transactions are not permitted. PCI-X Rev 1.0 -1.10.4
ERR7 (*Not implemented*) Initiator should driver address four clock before asserting frame in configuration
transactions
ERR8 PERR can not be asserted during attribute phase. PCI-X Rev 1.0 -1.10.6
ERR9 For I/O and memory DWORD transactions, AD0 and AD1 must match the byte enable. PCI-X Rev 1.0 -2.3
ERR10 In attribute phase reserved bits must be zero. PCI-X Rev 1.0 -2.5
ERR11 Initiators must not generate reserved commands. PCI-X Rev 1.0 -2.6
ERR12 After the attribute phase and during the data phase(s) of a transaction, the C/BE bus is reserved and must be driven
high by the initiator for all transactions except Memory Write. PCI-X Rev 1.0 -2.6
ERR13 DEVSEL can not be asserted 1, 5 or more than 6 clocks after address phase. PCI-X Rev 1.0 -2.8
ERR14 If the completer sets the Split Completion Error (SCE) bit in attribute phase, it must set also the Split Completion
Message (SCM) bit to indicate the Split Completion has message. PCI-X Rev 1.0 -2.10.4
ERR15 (*Not implemented*) If the transaction is a Split Completion Messages, the Lower Address field in the Split
Completion address must be set to zero, and the Byte Count field in the Completer Attributes must be set to four.
PCI-X Rev 1.0 -2.10.6
ERR16 (*Not implemented*) Delayed transactions not allowed.
ERR17 Memory write and Split Completion can not be completed as Split Transaction. PCI-X Rev 1.0 -1.7
ERR18 Initiator can not signal Master Abort before 8 clocks after assertion of FRAME. PCI-X Rev 1.0 -1.10.2
ERR19 The initiator must terminate the transaction when the byte count is satisfied. PCI-X Rev 1.0 -1.10.2,
ERR20 The initiator is permitted to disconnect a burst transaction (before the byte count is satisfied) only on an ADB.
PCI-X Rev 1.0 -1.10.2