Table 10-14. master clock input selection, Gtccr1, Ster 1 – Rainbow Electronics DS26519 User Manual
Page 136
DS26519 16-Port T1/E1/J1 Transceiver
136 of 310
Register Name:
GTCCR1
Register Description:
Global Transceiver Clock Control Register 1
Register Address:
00F3h
Channels:
1 to 8
Bit
# 7 6 5 4 3 2
1
0
Name
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL MPS1
MPS0
Default
0 0 0 0 0 0
0
0
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock
source will be used for BPCLK1 generation. The BPCLKn pin can be generated from the LIU’s 1 to 8 recovered
clocks, an external reference, or derivatives of MCLK input. This is shown in
additional information.
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
reference clock frequency used by the DS26519 backplane clock generation circuit. Note that the setting of this bit
should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock.
See
for additional information.
0 = Backplane reference clock is 2.048MHz.
1 = Backplane reference clock is 1.544MHz.
Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK
frequency of the signal input at the MCLK pin of the DS26519.
0 = The external master clock is 2.048MHz or multiple thereof.
1 = The external master clock is 1.544MHz or multiple thereof.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequency of the signal input at the MCLK pin of the DS26519. This is shown in
Table 10-14. Master Clock Input Selection
FREQSEL MPS1 MPS0
MCLK
(MHz ±50ppm)
0 0
0
2.048
0 0
1
4.096
0 1
0
8.192
0 1
1
16.384
1 0
0
1.544
1 0
1
3.088
1 1
0
6.176
1 1
1
12.352