2 path code violation count register (pcvcr), 3 frames out of sync count register (foscr), 4 e-bit counter (ebcr) – Rainbow Electronics DS26519 User Manual
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DS26519 16-Port T1/E1/J1 Transceiver
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9.9.9.2 Path Code Violation Count Register (PCVCR)
In T1 operation, the Path Code Violation Count Register records either Ft, Fs, or CRC-6 errors. When the receive
side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC-6 codewords.
When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the
.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be
disabled during receive loss of synchronization (RLOF = 1) conditions. See
for a detailed description of
exactly what errors the PCVCR counts in T1 operation.
In E1 operation, the Path Code Violation Count Register records CRC-4 errors. Since the maximum CRC-4 count
in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either
the FAS or CRC-4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
The Path Code Violation Count Register 1 (
) is the most significant word and the Path Code Violation
Count Register 2 (
) is the least significant word of a 16-bit counter that records path violations (PVs).
Table 9-30. T1 Path Code Violation Counting Arrangements
FRAMING MODE
COUNT Fs ERRORS?
WHAT IS COUNTED IN
,
D4
No
Errors in the Ft pattern
D4
Yes
Errors in both the Ft and Fs patterns
ESF
Don’t Care
Errors in the CRC-6 codewords
9.9.9.3 Frames Out of Sync Count Register (FOSCR)
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is
useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events
as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during
receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will
count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF
mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOF = 1)
conditions. See
for a detailed description of what the FOSCR is capable of counting.
In E1 mode, the FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled
when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or
synchronization at either the CAS or CRC-4 multiframe level. Since the maximum FAS word error count in a one-
second period is 4000, this counter cannot saturate.
The Frames Out of Sync Count Register 1 (
) is the most significant word and the Frames Out of Sync
Count Register 2
is the least significant word of a 16-bit counter that records frames out of sync.
Table 9-31. T1 Frames Out of Sync Counting Arrangements
FRAMING MODE
COUNT MOS OR F-BIT ERRORS
(
WHAT IS COUNTED
IN
,
D4
MOS
Number of multiframes out of sync
D4
F-Bit
Errors in the Ft pattern
ESF
MOS
Number of multiframes out of sync
ESF
F-Bit
Errors in the FPS pattern
9.9.9.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. The E-Bit Count Register 1 (
) is the most significant word and
the E-Bit Count Register 2 (
) is the least significant word of a 16-bit counter that records far-end block
errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These
count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a
one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the
FAS or CRC-4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.