Rainbow Electronics DS26519 - Manual (Page 84)

DS26519 16-Port T1/E1/J1 Transceiver
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9.10 HDLC Controllers
9.10.1 Receive HDLC Controller
This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). The HDLC controller has 64-byte FIFO buffer in both the transmit and receive paths.
The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa
bits (E1 mode).
The HDLC controller performs all the necessary overhead for generating and receiving performance report
messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 9-36 shows the registers related to the HDLC.
Table 9-36. Registers Related to the HDLC
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive HDLC Control Register ( RHC ) 010h Mapping of the HDLC to DS0 or FDL.
Receive HDLC Bit Suppress Register
(
RHBSE )
011h Receive HDLC bit suppression register.
Receive HDLC FIFO Control Register
(
RHFC )
087h
Determines the length of the receive HDLC
FIFO.
Receive HDLC Packet Bytes Available
Register (
RHPBA )
0B5h
Tells the user how many bytes are available in
the teceive HDLC FIFO.
Receive HDLC FIFO Register ( RHF ) 0B6h The actual FIFO data.
Receive Real-Time Status Register 5
(
RRTS5 )
0B4h Indicates the FIFO status.
Receive Latched Status Register 5 ( RLS5 ) 094h Latched status.
Receive Interrupt Mask Register 5 ( RIM5 ) 0A4h
Interrupt mask for interrupt generation for the
latched status.
Transmit HDLC Control Register 1( THC1 ) 110h Miscellaneous transmit HDLC control.
Transmit HDLC Bit Suppress Register
(
THBSE )
111h
Transmit HDLC bit suppress for bits not to be
used.
Transmit HDLC Control Register 2 ( THC2 ) 113h
HDLC to DS0 channel selection and other
control.
Transmit HDLC FIFO Control Register
(
THFC )
187h Used to control the transmit HDLC FIFO.
Transmit Real-Time Status Register 2
(
TRTS2 )
1B1h
Indicates the real-time status of the transmit
HDLC FIFO.
Transmit HDLC Latched Status Register 2
(
TLS2 )
191h Indicates the FIFO status.
Transmit Interrupt Mask Register 2 (HDLC)
Register (
TIM2 )
1A1h Interrupt mask for the latched status.
Transmit HDLC FIFO Buffer Available
Register (
TFBA )
1B3h
Indicates the number of bytes that can be
written into the transmit FIFO.
Transmit HDLC FIFO Register ( THF ) 1B4h Transmit HDLC FIFO.
Note: The addresses shown are for Framer 1.