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Receive idle code definition registers 1 to 32, T1rbocc, Register – Rainbow Electronics DS26519 User Manual

Page 161: Ridr1

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DS26519 16-Port T1/E1/J1 Transceiver

161 of 310

Register Name:

T1RBOCC (T1 Mode Only)

Register Description:

Receive BOC Control Register

Register Address:

015h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16


Bit

# 7 6 5 4 3 2 1 0

Name RBR — RBD1

RBD0 — RBF1

RBF0 —

Default

0 0 0 0 0 0 0 0


Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is
an acknowledged reset—that is, the host needs only to set the bit and the DS26519 will clear it once the reset
operation is complete (less than 250

μs). Modifications to the RBF[1:0] and RBD[1:0] bits will not be applied to the

BOC controller until a BOC reset has been completed.

Bits 5 and 4: Receive BOC Disintegration Bits (RBD[1:0]). The BOC disintegration filter sets the number of
message bits that must be received without a valid BOC to set the BC bit indicating that a valid BOC is no longer
being received.

RBD1 RBD0

CONSECUTIVE MESSAGE BITS

FOR BOC CLEAR IDENTIFICATION

0 0

16

0 1

32

1 0

48

1

1

64 (See Note 1)


Bits 2 and 1: Receive BOC Filter Bits (RBF[1:0).
The BOC filter sets the number of consecutive patterns that
must be received without error prior to an indication of a valid message.

RBF1 RBF0

CONSECUTIVE BOC CODES FOR

VALID SEQUENCE IDENTIFICATION

0 0

None

0 1

3

1 0

5

1 1

7

(See Note 1)

Note 1: The DS26519’s BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration
time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be
detected.





Register Name:

RIDR1 to RIDR32

Register Description:

Receive Idle Code Definition Registers 1 to 32

Register Address:

020h to 03Fh + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16


Bit

# 7 6 5 4 3 2 1 0

Name

C7 C6 C5 C4 C3 C2 C1 C0

Default

0 0 0 0 0 0 0 0


Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
20h is for channel 1. Address 37h is for channel 24. Address 3Fh is for channel 32. RIDR25–RIDR32 are E1 mode
only.