causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The
transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as
SBOC is set. Note that the TFPT (

TCR1

.6) control bit must be set to zero for the BOC message to overwrite F-bit

information being sampled on TSERn.

9.9.5.1.1 To Transmit a BOC

1) Write 6-bit code into the

T1TBOC

2) Set SBOC bit in

THC2

= 1.

9.9.5.2 Receive Bit-Oriented Code (BOC) Controller

The DS26528 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The
BOC function is available only in T1, ESF mode in the data link bits.

Table 9-20

shows the registers related to the

receive BOC operation.

Table 9-20. Registers Related to T1 Receive BOC

REGISTER

FRAMER 1

ADDRESSES

FUNCTION

Receive BOC Control Register
(

T1RBOCC

)

015h

Controls the receive BOC function.

Receive BOC Register (

T1RBOC

)

063h

Receive bit-oriented message.

Receive Latched Status Register 7(

RLS7

) 096h

Indicates changes to the receive bit-oriented
messages.

Receive Interrupt Mask Register 7 (

RIM7

) 0A6h

Mask bits for RBOC for generation of
interrupts.

Note: The addresses shown above are for Framer 1.

In ESF mode, the DS26519 continuously monitors the receive message bits for a valid BOC message. The BOC
detect (BD) status bit at

RLS7

.0 will be set once a valid message has been detected for time determined by the

receive BOC filter bits RBF0 and RBF1 in the

T1RBOCC

RBOC register. Once the user has cleared the BD bit, it will remain clear until a new BOC is detected (or the same
BOC is detected following a BOC clear event). The BOC clear (BC) bit at

RLS7

.1 is set when a valid BOC is no

longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the

T1RBOCC

The BD and BC status bits can create a hardware interrupt on the

INTB signal as enabled by the associated

interrupt mask bits in the

RIM7