Rainbow Electronics DS26519 - Manual (Page 306)

DS26519 16-Port T1/E1/J1 Transceiver
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14.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH moves the controller to
the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS26519 and its respective operational binary codes are
shown in
Table 14-1 .
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SELECTED REGISTER INSTRUCTION CODES
SAMPLE:PRELOAD Boundary Scan 010
BYPASS Bypass 111
EXTEST Boundary Scan 000
CLAMP Bypass 011
HIGHZ Bypass 100
IDCODE Device Identification 001
14.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the Boundary Scan Register without interfering with the normal
operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into
the boundary scan register via JTDI using the Shift-DR state.
14.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit Bypass Test Register. This allows data to pass from JTDI to JTDO without affecting the device’s normal
operation.
14.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins will be driven. The Boundary Scan Register will be connected between JTDI and JTDO. The Capture-DR will
sample all digital inputs into the Boundary Scan Register.
14.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
14.2.5 HIGHZ
All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected
between JTDI and JTDO.
14.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a “1” in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version.