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Tim3, Tim2, Interrupts will forc – Rainbow Electronics DS26519 User Manual

Page 243

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DS26519 16-Port T1/E1/J1 Transceiver

243 of 310

Register Name:

TIM2

Register Description:

Transmit Interrupt Mask Register 2

Register Address:

1A1h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16


Bit

# 7 6 5 4 3 2 1 0

Name — — — TFDLE

TUDR

TMEND

TLWMS

TNFS

— TUDR

TMEND

TLWMS

TNFS

Default

0 0 0 0 0 0 0 0


Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only)

0 = Interrupt masked.
1 = Interrupt enabled.

Bit 3: Transmit FIFO Underrun Event (TUDR)

0 = Interrupt masked.
1 = Interrupt enabled.

Bit 2: Transmit Message End Event (TMEND)

0 = Interrupt masked.
1 = Interrupt enabled.

Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS)

0 = Interrupt masked.
1 = Interrupt enabled.

Bit 0: Transmit FIFO Not Full Set Condition (TNFS)

0 = Interrupt masked.
1 = Interrupt enabled.



Register Name:

TIM3

Register Description:

Transmit Interrupt Mask Register 3 (Synchronizer)

Register Address:

1A2h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16


Bit

# 7 6 5 4 3 2 1 0

Name

— — — — — — —

LOFD

Default

0 0 0 0 0 0 0 0


Bit 0: Loss Of Frame Synchronization Detect (LOFD)

0 = Interrupt masked.
1 = Interrupt enabled.