Rainbow Electronics DS26519 - Manual (Page 87)

DS26519 16-Port T1/E1/J1 Transceiver
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9.10.2 Transmit HDLC Controller
9.10.2.1 FIFO Information
The Transmit HDLC FIFO Buffer Available Register ( TFBA ) indicates the number of bytes that can be written into
the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
9.10.2.2 HDLC Transmit Example
The HDLC status registers in the DS26519 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
Figure 9-19 shows an example routine
for using the DS26519 HDLC receiver.