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Feature highlights, 1 general, 2 line interface – Rainbow Electronics DS26519 User Manual

Page 10: 3 clock synthesizers, 4 jitter attenuator, Eneral, Nterface, Lock, Ynthesizers, Itter

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DS26519 16-Port T1/E1/J1 Transceiver

10 of 310

2. FEATURE

HIGHLIGHTS

2.1 General

23mm x 23mm, 484-pin HSBGA (1.00mm pitch)
3.3V and 1.8V supply with 5V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Development support includes evaluation kit, driver source code, and reference designs

2.2 Line

Interface

Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,

2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz.

Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to

30dB, 0dB to 20dB, and 0dB to -15dB for T1

Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB

increments

Software-selectable receive termination for 75

Ω, 100Ω, 110Ω, and 120Ω lines

Hitless protection switching
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75

Ω coax and 120Ω twisted cables

Analog loss-of-signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmit outputs and receive inputs present a high impedance to the line when no power is applied,

supporting redundancy applications

Transmitter short-circuit limiter with current-limit-exceeded indication
Transmit open-circuit-detected indication

2.3 Clock

Synthesizers

Backplane clocks output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz

− Derived from user-selected recovered receive clock or REFCLKIO

CLKO output clock selectable from a wide range of frequencies referenced to MCLK

2.4 Jitter

Attenuator

32-bit or 128-bit crystal-less jitter attenuator
Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication