T1.tcr2, 6 (tslc96, D with – Rainbow Electronics DS26519 User Manual
Page 230: 7, the transmit, Rls3, 7 tfdls mu, By tb7zs
DS26519 16-Port T1/E1/J1 Transceiver
230 of 310
Register Name:
T1.TCR2 (T1 Mode)
Register Description:
Transmit Control Register 2
Register Address:
182h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
Bit
# 7 6 5 4 3 2 1 0
Name TFDLS
TSLC96
TDDSEN
FBCT2 FBCT1 TRAIS — TB7ZS
Default
0 0 0 0 0 0 0 0
Note: See
for E1 Mode.
Bit 7: TFDL Register Select (TFDLS)
0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (
1 = Source FDL or Fs bits from the internal HDLC controller.
Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the
–3 registers. See Section
0 = SLC-96 insertion disabled.
1 = SLC-96 insertion enabled.
Bit 5: Transmit DDS Zero Suppression Enable (TDDSEN)
0 = No DDS stuffing.
1 = DDS stuffing enabled. Force zero code 10011000 in all zero byte channels based on the channel
select registers
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit RAI Select (TRAIS)
0 = Transmit RAI is T1.
D4—Zeros in bit 2 of all channels.
ESF—00FF pattern in the FDL.
1 = Transmit RAI is J1.
D4—A one in the S-bit position of frame 12.
ESF—All ones in FDL.
Note: This bit only selects the type of remote alarm to send. To enable transmission of remote alarm, set
Bit 0: Transmit-Side Bit 7 Zero Suppression Enable (TB7ZS)
0 = No stuffing occurs.
1 = Force bit 7 to a one as determined by the GB7S bit at
.3.