Rainbow Electronics DS26519 - Manual (Page 184)

DS26519 16-Port T1/E1/J1 Transceiver
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Register Name: ERCNT
Register Description: Error Counter Configuration Register
Register Address: 086h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
Bit
# 7 6 5 4 3 2 1 0
Name 1SECS MCUS MECU ECUS EAMS FSBE MOSCRF LCVCRF
1SECS MCUS MECU ECUS EAMS — — LCVCRF
Default 0 0 0 0 0 0 0 0
Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between
multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer’s error counters on
the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1.
0 = Use the one-second timer that is internal to the framer.
1 = Use the one-second timer from framer 1 to latch updates.
Bit 6 : Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be
used to allow the incoming LATCH_CNT signal to latch all counters. Useful for synchronously latching counters of
multiple DS26519 cores located on the same die.
0 = MECU is used to manually latch counters.
1 = Counters are latched on the rising edge of the LATCH_CNT signal.
Bit 5: Manual Error Counter Update (MECU). When enabled by
ERCNT .3, the changing of this bit from a 0 to a 1
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
user must wait a minimum of 250
μs before reading the error count registers to allow for proper update.
Bit 4: Error Counter Update Select (ECUS)
T1 mode:
0 = Update error counters once a second.
1 = Update error counters every 42ms (333 frames).
E1 mode:
0 = Update error counters once a second.
1 = Update error counters every 62.5ms (500 frames).
Bit 3: Error Accumulation Mode Select (EAMS)
0 = Automatic updating of error counters enabled. The state of ERCNT .4 determines accumulation time
(timed update).
1 = User toggling of ERCNT.5 determines accumulation time (manual update).
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only)
0 = Do not report bit errors in Fs-bit position; only Ft-bit position.
1 = Report bit errors in Fs-bit position as well as Ft-bit position.
Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only)
0 = Count errors in the framing bit position.
1 = Count the number of multiframes out of sync.
Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF)
0 = Do not count excessive zeros.
1 = Count excessive zeros.