Rls7, 0 will b, Bit at – Rainbow Electronics DS26519 User Manual
Page 194: 2 bit. if, 1 (sa6, Registe, Interrupt in, 0, the u
DS26519 16-Port T1/E1/J1 Transceiver
194 of 310
Register Name:
RLS7 (T1 Mode)
Register Description:
Receive Latched Status Register 7
Register Address:
096h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
Bit
# 7 6 5 4 3 2 1 0
Name — —
RRAI-CI
RAIS-CI
RSLC96
RFDLF
BC BD
Default
0 0 0 0 0 0 0 0
Note: All bits in this register are latched and can create interrupts. See
Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is
active in ESF framing mode only, and will set only if an RAI condition is being detected (
.3). When the host
reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1
seconds).
Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit
will set only if an AIS condition is being detected (
.2). This is a latched bit that must be cleared by the host,
and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds).
Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the
Fs bit stream, and the
–3 registers have data available for retrieval. See Section
information.
Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit
register is full. Useful for SLC-96
operation, or manual extraction of FDL data bits. See Section
for more information.
Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied).
Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied).
Register Name:
RLS7 (E1 Mode)
Register Description:
Receive Latched Status Register 7
Register Address:
096h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
Bit
# 7 6 5 4 3 2 1 0
Name
— — — — — —
Sa6CD
SaXCD
Default
0 0 0 0 0 0 0 0
Note: All bits in this register are latched and can create interrupts. See
for T1 Mode.
Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit
positions.
Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled
SaX bits are selected by the
register.