Rls3, Normally – Rainbow Electronics DS26519 User Manual
Page 190
DS26519 16-Port T1/E1/J1 Transceiver
190 of 310
Register Name:
RLS3 (T1 Mode)
Register Description:
Receive Latched Status Register 3
Register Address:
092h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
Bit
# 7 6 5 4 3 2 1 0
Name LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD
Default
0 0 0 0 0 0 0 0
Note: All bits in this register are latched and can create interrupts. See
Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC
condition was detected and then removed.
Bit 6: Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match
condition was detected and then removed.
Bit 5: Loop Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down
condition was detected and then removed
Bit 4: Loop Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up
condition was detected and then removed.
Bit 3: Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLKn pin
has not transitioned for one channel time.
Bit 2: Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as
defined in the
:
registers is being received.
Bit 1: Loop Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loop down
code as defined in the
:
register is being received.
Bit 0: Loop Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop up code
as defined in the
:
register is being received.