2 sa-bit monitoring and reporting, 7 maintenance and alarms, Maintenance and alarms – Rainbow Electronics DS26519 User Manual
Page 72
DS26519 16-Port T1/E1/J1 Transceiver
72 of 310
9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode)
The DS26519, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods.
The first involves using the internal
/
registers. The second method involves
an expanded version of the first method.
9.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1)
On the receive side, the
registers will always report the data as it received in the Sa and Si bit
locations. The
and
registers are updated on align frame boundaries. The setting of the Receive
Align Frame bit in Receive Latched Status Register 2 (
.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the
.0 bit to know when to read the
registers. The
host has 250
μs to retrieve the data before it is lost.
9.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive)
On the receive side, there is a set of eight registers (
,
,
to E1RSa8) that report
the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in Receive Latched Status Register 2 (
.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for
additional information.
9.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit)
On the transmit side there is a set of eight registers (
,
,
) that, via
the E1 Transmit Sa-Bit Control Register (
), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1
(
.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or
else the old data will be retransmitted. See the register descriptions in Section
for more information.
9.9.6.2 Sa-Bit Monitoring and Reporting
In addition to the registers outlined above, the DS26519 provides status and interrupt capability in order to detect
changes in the state of selected Sa bits. The
register can be used to select which Sa bits are
monitored for a change of state. When a change of state is detected in one of the enabled Sa bit positions, a status
bit is set in the
RLS7
register via the SaXCD bit (bit 0). This status bit can in turn be used to generate an interrupt
by unmasking
.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the
register at
address 06Eh to determine the current value of each Sa bit.
For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE
register will report the received Sa6 codeword. The codeword must be stable for a period of three submultiframes
and be different from the previous stored value in order to be updated in this register. See the
Sa6CODE
register
description for further details on the operation of this register and the values reported in it. An additional status bit is
provided in
.1 (Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this
status bit in
RIM7
to allow for interrupt generation when enabled.
9.9.7 Maintenance and Alarms
The DS26519 provides extensive functions for alarm detection and generation. It also provides diagnostic functions
for monitoring of performance and sending of diagnostic information:
• Real-time and latched status bits, interrupts and interrupt mask for transmitter and receiver
• LOS detection
• RIA detection and generation
• Error counters
• DS0 monitoring
• Milliwatt generation and detection
• Slip buffer status for transmit and receive