Rainbow Electronics DS26519 - Manual (Page 2)

DS26519 16-Port T1/E1/J1 Transceiver
2 of 310
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9
2. FEATURE HIGHLIGHTS ..................................................................................................10
2.1 G ENERAL ......................................................................................................................................10
2.2 L INE I NTERFACE ............................................................................................................................10
2.3 C LOCK S YNTHESIZERS ..................................................................................................................10
2.4 J ITTER A TTENUATOR .....................................................................................................................10
2.5 F RAMER /F ORMATTER ....................................................................................................................11
2.6 S YSTEM I NTERFACE ......................................................................................................................11
2.7 HDCL C ONTROLLERS ...................................................................................................................12
2.8 T EST AND D IAGNOSTICS ................................................................................................................12
2.9 M ICROCONTROLLER P ARALLEL P ORT .............................................................................................12
2.10 S LAVE S ERIAL P ERIPHERAL I NTERFACE (SPI) F EATURES ............................................................12
3. APPLICATIONS ...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE ...................................................................................14
5. ACRONYMS AND GLOSSARY .......................................................................................16
6. MAJOR OPERATING MODES.........................................................................................17
7. BLOCK DIAGRAMS.........................................................................................................18
8. PIN DESCRIPTIONS ........................................................................................................20
8.1 P IN F UNCTIONAL D ESCRIPTION ......................................................................................................20
9. FUNCTIONAL DESCRIPTION .........................................................................................33
9.1 P ROCESSOR I NTERFACE ................................................................................................................33
9.1.1 SPI Serial Port Mode............................................................................................................................ 33
9.1.2 SPI Functional Timing Diagrams ......................................................................................................... 33
9.2 C LOCK S TRUCTURE .......................................................................................................................35
9.2.1 Backplane Clock Generation ............................................................................................................... 35
9.2.2 CLKO Output Clock Generation........................................................................................................... 37
9.3 R ESETS AND P OWER -D OWN M ODES ..............................................................................................38
9.4 I NITIALIZATION AND C ONFIGURATION ..............................................................................................39
9.4.1 Example Device Initialization and Sequence ....................................................................................... 39
9.5 G LOBAL R ESOURCES ....................................................................................................................40
9.5.1 General-Purpose I/O Pins .................................................................................................................... 40
9.6 P ER -P ORT R ESOURCES ................................................................................................................40
9.7 D EVICE I NTERRUPTS .....................................................................................................................41
9.8 S YSTEM B ACKPLANE I NTERFACE ...................................................................................................43
9.8.1 Elastic Stores ....................................................................................................................................... 43
9.8.2 IBO Multiplexing ................................................................................................................................... 46
9.8.3 H.100 (CT Bus) Compatibility .............................................................................................................. 55
9.8.4 Transmit and Receive Channel Blocking Registers............................................................................. 57
9.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 57
9.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 57
9.9 F RAMERS ......................................................................................................................................58
9.9.1 T1 Framing........................................................................................................................................... 58
9.9.2 E1 Framing........................................................................................................................................... 61
9.9.3 T1 Transmit Synchronizer .................................................................................................................... 63
9.9.4 Signaling .............................................................................................................................................. 64
9.9.5 T1 Data Link......................................................................................................................................... 69
9.9.6 E1 Data Link......................................................................................................................................... 71