Epson S1C33210 - Manual (Page 69)

4 PERIPHERAL CIRCUITS
S1C33210 PRODUCT PART EPSON A-55
Name Address Register name Bit Function Setting Init. R/W Remarks
TC3_L7
TC3_L6
TC3_L5
TC3_L4
TC3_L3
TC3_L2
TC3_L1
TC3_L0
BLKLEN37
BLKLEN36
BLKLEN35
BLKLEN34
BLKLEN33
BLKLEN32
BLKLEN31
BLKLEN30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer counter[7:0]
(block transfer mode)
Ch.3 transfer counter[15:8]
(single/successive transfer mode)
Ch.3 block length
(block transfer mode)
Ch.3 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048250
(HW)
High-speed
DMA Ch.3
transfer
counter
register
–
–
DUALM3
D3DIR
–
TC3_H7
TC3_H6
TC3_H5
TC3_H4
TC3_H3
TC3_H2
TC3_H1
TC3_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 address mode selection
D) Invalid
S) Ch.3 transfer direction control
reserved
Ch.3 transfer counter[15:8]
(block transfer mode)
Ch.3 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1 Memory WR 0 Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048252
(HW)
High-speed
DMA Ch.3
control register
Note:
D) Dual address
mode
S) Single
address
mode
S3ADRL15
S3ADRL14
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 source address[15:0]
S) Ch.3 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W 0048254
(HW)
High-speed
DMA Ch.3
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE3
S3IN1
S3IN0
S3ADRH11
S3ADRH10
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transfer data size
D) Ch.3 source address control
S) Ch.3 memory address control
D) Ch.3 source address[27:16]
S) Ch.3 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048256
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.3
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–