Epson S1C33210 - Manual (Page 543)

APPENDIX: I/O MAP
S1C33210 FUNCTION PART EPSON B-APPENDIX-35
Name Address Register name Bit Function Setting Init. R/W Remarks
TC0_L7
TC0_L6
TC0_L5
TC0_L4
TC0_L3
TC0_L2
TC0_L1
TC0_L0
BLKLEN07
BLKLEN06
BLKLEN05
BLKLEN04
BLKLEN03
BLKLEN02
BLKLEN01
BLKLEN00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer counter[7:0]
(block transfer mode)
Ch.0 transfer counter[15:8]
(single/successive transfer mode)
Ch.0 block length
(block transfer mode)
Ch.0 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048220
(HW)
High-speed
DMA Ch.0
transfer
counter
register
–
–
DUALM0
D0DIR
–
TC0_H7
TC0_H6
TC0_H5
TC0_H4
TC0_H3
TC0_H2
TC0_H1
TC0_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 address mode selection
D) Invalid
S) Ch.0 transfer direction control
reserved
Ch.0 transfer counter[15:8]
(block transfer mode)
Ch.0 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1 Memory WR 0 Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048222
(HW)
High-speed
DMA Ch.0
control register
Note:
D) Dual address
mode
S) Single
address
mode
S0ADRL15
S0ADRL14
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 source address[15:0]
S) Ch.0 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W 0048224
(HW)
High-speed
DMA Ch.0
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE0
S0IN1
S0IN0
S0ADRH11
S0ADRH10
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.0 transfer data size
D) Ch.0 source address control
S) Ch.0 memory address control
D) Ch.0 source address[27:16]
S) Ch.0 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048226
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.0
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–