Epson S1C33210 - Manual (Page 428)

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
B-III-10-42 EPSON S1C33210 FUNCTION PART
Important Notes on Debugging
ICD33 debugging mode supports the use of the ICD33MODE signal from the CPU core to hold certain
communications block input signals at their current levels and thus simulate suspension of communications.
Setting the STOP bit in the communications block debugging mode register (D0/0x0200032) to "1" holds the CTS,
DCD, and RXD inputs at their current levels when the internal signal indicating ICD33 debugging mode goes active.
Communications therefore stops in a state that appears equivalent to stopping the clock.
Setting the STOP bit to "0" produces normal communications interface operation even in ICD33 debugging mode.
Note that the only inputs that the STOP bit controls this way are the three given above.