Epson S1C33210 User Manual
Page 477
V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33210 FUNCTION PART
EPSON
B-V-2-25
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
D2MOD1
D2MOD0
D2IN1
D2IN0
D2ADRH11
D2ADRH10
D2ADRH9
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer mode
D) Ch.2 destination address
control
S) Invalid
D) Ch.2 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004824A
(HW)
High-speed
DMA Ch.2
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D2MOD[1:0]
Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D2IN[1:0]
Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
–
HS2_EN
DF–1
D0
reserved
Ch.2 enable
1 Enable
0 Disable
–
0
–
R/W
Undefined in read.
004824C
(HW)
High-speed
DMA Ch.2
enable register
–
–
HS2_TF
DF–1
D0
reserved
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading)
1 Clear
0 No operation
1 Set
0 Cleared
–
0
–
R/W
Undefined in read.
004824E
(HW)
High-speed
DMA Ch.2
trigger flag
register
TC3_L7
TC3_L6
TC3_L5
TC3_L4
TC3_L3
TC3_L2
TC3_L1
TC3_L0
BLKLEN37
BLKLEN36
BLKLEN35
BLKLEN34
BLKLEN33
BLKLEN32
BLKLEN31
BLKLEN30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer counter[7:0]
(block transfer mode)
Ch.3 transfer counter[15:8]
(single/successive transfer mode)
Ch.3 block length
(block transfer mode)
Ch.3 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048250
(HW)
High-speed
DMA Ch.3
transfer
counter
register
–
–
DUALM3
D3DIR
–
TC3_H7
TC3_H6
TC3_H5
TC3_H4
TC3_H3
TC3_H2
TC3_H1
TC3_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 address mode selection
D) Invalid
S) Ch.3 transfer direction control
reserved
Ch.3 transfer counter[15:8]
(block transfer mode)
Ch.3 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr
0 Single addr
1 Memory WR 0 Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048252
(HW)
High-speed
DMA Ch.3
control register
Note:
D) Dual address
mode
S) Single
address
mode