beautypg.com

Epson S1C33210 User Manual

Page 214

background image

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-16

EPSON

S1C33210 FUNCTION PART

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

HSD1S3

HSD1S2

HSD1S1

HSD1S0

HSD0S3

HSD0S2

HSD0S1

HSD0S0

D7

D6

D5

D4

D3

D2

D1

D0

High-speed DMA Ch.1

trigger set-up

High-speed DMA Ch.0

trigger set-up

0

0

0

0

0

0

0

0

R/W

R/W

0040298

(B)

0

1

2

3

4

5

6

7

8

9

A

B

C

Software trigger

K51 input (falling edge)

K51 input (rising edge)

Port 1 input

Port 5 input

8-bit timer Ch.1 underflow

16-bit timer Ch.1 compare B

16-bit timer Ch.1 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

0

1

2

3

4

5

6

7

8

9

A

B

C

Software trigger

K50 input (falling edge)

K50 input (rising edge)

Port 0 input

Port 4 input

8-bit timer Ch.0 underflow

16-bit timer Ch.0 compare B

16-bit timer Ch.0 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.0/1

trigger set-up

register

HSD3S3

HSD3S2

HSD3S1

HSD3S0

HSD2S3

HSD2S2

HSD2S1

HSD2S0

D7

D6

D5

D4

D3

D2

D1

D0

High-speed DMA Ch.3

trigger set-up

High-speed DMA Ch.2

trigger set-up

0

0

0

0

0

0

0

0

R/W

R/W

0040299

(B)

0

1

2

3

4

5

6

7

8

9

A

B

C

Software trigger

Port 3 input

Port 7 input

8-bit timer Ch.3 underflow

16-bit timer Ch.3 compare B

16-bit timer Ch.3 compare A

16-bit timer Ch.5 compare B

16-bit timer Ch.5 compare A

SI/F Ch.1 Rx buffer full

SI/F Ch.1 Tx buffer empty

A/D conversion completion

0

1

2

3

4

5

6

7

8

9

A

B

C

Software trigger

Port 2 input

Port 6 input

8-bit timer Ch.2 underflow

16-bit timer Ch.2 compare B

16-bit timer Ch.2 compare A

16-bit timer Ch.4 compare B

16-bit timer Ch.4 compare A

SI/F Ch.0 Rx buffer full

SI/F Ch.0 Tx buffer empty

A/D conversion completion

High-speed

DMA Ch.2/3

trigger set-up

register

DENONLY

IDMAONLY

RSTONLY

D7–3

D2

D1

D0

reserved

IDMA enable register set method

selection

IDMA request register set method

selection

Interrupt factor flag reset method

selection

1

1

1

R/W

R/W

R/W

004029F

(B)

Flag set/reset

method select

register

1 Set only

0 RD/WR

1 Set only

0 RD/WR

1 Reset only

0 RD/WR